[PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)

[Paul Brook]

> > > Richard, what do you think?
> 
> The ARM compiler only supports limiting the length of an LDM sequence to
> not more than 4 registers if the register *loads* the PC and not more
> than 5 registers in all other cases.  The goal is to bound the latency
> of the instruction without getting stupid about overall-code bloat.  I'm
> not keen on the idea of banning all ldm sequences -- some
> prologue/epilogue code gets quite ugly if you try to do that.
> Additionally, cores without caches normally perform ldm/stm much more
> efficiently than individual loads, so it can cost significant extra
> overall time in that case.

I believe it was LDM/STM specifically that motivated this change. IIUC the 
third party cores effectively microcode these. A side-effect of this is that 
they are never faster[1] and interact badly with the cache subsystem. A 
TLB/cache miss can block interrupts for a long time while waiting for external 
RAM. A single ldr can be aborted and the IRQ processed immediately[2].  I 
don't know whether this is true on cores supported by FSF gcc.

Paul

[1] Ignoring increased icache footprint.
[2] Assume the IRQ handler is either locked into cache or in fast local RAM.