[PATCH, i386]: Further macroization of add patterns.
Uros Bizjak
ubizjak@gmail.com
Fri Jun 4 11:51:00 GMT 2010
Hello!
After pic_symbolic_operand predicate removal [1], we can macroize add
patterns some more. It should be noted, that QImode operand can not
have integer value of 255, so we are safe to assert exception for
operand[2] == 255. On a related note, QImode operand also can't have
integer value of 128, so we can safely macroize insn patterns together
with QImode insns.
2010-06-04 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*addqi_2): Do not assert operands[2] == 255
for TYPE_INCDEC operands.
(*addqi_3): Ditto.
(*addqi_4): Ditto.
(*addqi_5): Ditto.
(*addqi_ext_1_rex64): Ditto.
(*addqi_ext_1): Ditto.
(*addqi_4): Check for incdec_operand in QImode.
(*add<mode>_2): Macroize insn from *add<mode>_2 and *add{qi,hi}_2
using SWI mode iterator.
(*add<mode>_3): Ditto from *add<mode>_3 and *add{qi,hi}_3.
(*add<mode>_4): Macroize insn from *add{qi,hi,si}_4 using SWI124
mode iterator.
(*add<mode>_5): Macroize insn from *add<mode>_5 and *add{qi,hi}_5
using SWI mode iterator.
Attached patch was bootstrapped and regression tested on
x86_64-pc-linux-gnu. Will be committed to SVN in a couple of hours.
[1] http://gcc.gnu.org/ml/gcc-patches/2010-06/msg00280.html
Uros.
-------------- next part --------------
Index: i386.md
===================================================================
--- i386.md (revision 160253)
+++ i386.md (working copy)
@@ -6395,12 +6395,12 @@
(define_insn "*add<mode>_2"
[(set (reg FLAGS_REG)
(compare
- (plus:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand" "%0,0")
- (match_operand:SWI48 2 "<general_operand>" "<g>,r<i>"))
+ (plus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
+ (match_operand:SWI 2 "<general_operand>" "<g>,<r><i>"))
(const_int 0)))
- (set (match_operand:SWI48 0 "nonimmediate_operand" "=r,rm")
- (plus:SWI48 (match_dup 1) (match_dup 2)))]
+ (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>,<r>m")
+ (plus:SWI (match_dup 1) (match_dup 2)))]
"ix86_match_ccmode (insn, CCGOCmode)
&& ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
{
@@ -6427,7 +6427,7 @@
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
@@ -6478,89 +6478,12 @@
(const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*addhi_2"
- [(set (reg FLAGS_REG)
- (compare
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
- (match_operand:HI 2 "general_operand" "rmn,rn"))
- (const_int 0)))
- (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
- (plus:HI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, HImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
- }
-
- default:
- if (x86_maybe_negate_const_int (&operands[2], HImode))
- return "sub{w}\t{%2, %0|%0, %2}";
-
- return "add{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-(define_insn "*addqi_2"
- [(set (reg FLAGS_REG)
- (compare
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
- (match_operand:QI 2 "general_operand" "qmn,qn"))
- (const_int 0)))
- (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
- (plus:QI (match_dup 1) (match_dup 2)))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && ix86_binary_operator_ok (PLUS, QImode, operands)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- if (x86_maybe_negate_const_int (&operands[2], QImode))
- return "sub{b}\t{%2, %0|%0, %2}";
-
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
(define_insn "*add<mode>_3"
[(set (reg FLAGS_REG)
(compare
- (neg:SWI48 (match_operand:SWI48 2 "<general_operand>" "<g>"))
- (match_operand:SWI48 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:SWI48 0 "=r"))]
+ (neg:SWI (match_operand:SWI 2 "<general_operand>" "<g>"))
+ (match_operand:SWI 1 "nonimmediate_operand" "%0")))
+ (clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_match_ccmode (insn, CCZmode)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
@@ -6587,7 +6510,7 @@
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
@@ -6637,79 +6560,6 @@
(const_string "*")))
(set_attr "mode" "SI")])
-(define_insn "*addhi_3"
- [(set (reg FLAGS_REG)
- (compare
- (neg:HI (match_operand:HI 2 "general_operand" "rmn"))
- (match_operand:HI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:HI 0 "=r"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
- }
-
- default:
- if (x86_maybe_negate_const_int (&operands[2], HImode))
- return "sub{w}\t{%2, %0|%0, %2}";
-
- return "add{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-(define_insn "*addqi_3"
- [(set (reg FLAGS_REG)
- (compare
- (neg:QI (match_operand:QI 2 "general_operand" "qmn"))
- (match_operand:QI 1 "nonimmediate_operand" "%0")))
- (clobber (match_scratch:QI 0 "=q"))]
- "ix86_match_ccmode (insn, CCZmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- if (x86_maybe_negate_const_int (&operands[2], QImode))
- return "sub{b}\t{%2, %0|%0, %2}";
-
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
; For comparisons against 1, -1 and 128, we may generate better code
; by converting cmp to add, inc or dec as done by peephole2. This pattern
; is matched then. We can't accept general immediate, because for
@@ -6763,35 +6613,35 @@
; Also carry flag is reversed compared to cmp, so this conversion is valid
; only for comparisons not depending on it.
-(define_insn "*addsi_4"
+(define_insn "*add<mode>_4"
[(set (reg FLAGS_REG)
(compare
- (match_operand:SI 1 "nonimmediate_operand" "0")
- (match_operand:SI 2 "const_int_operand" "n")))
- (clobber (match_scratch:SI 0 "=rm"))]
+ (match_operand:SWI124 1 "nonimmediate_operand" "0")
+ (match_operand:SWI124 2 "const_int_operand" "n")))
+ (clobber (match_scratch:SWI124 0 "=<r>m"))]
"ix86_match_ccmode (insn, CCGCmode)"
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == constm1_rtx)
- return "inc{l}\t%0";
+ return "inc{<imodesuffix>}\t%0";
else
{
gcc_assert (operands[2] == const1_rtx);
- return "dec{l}\t%0";
+ return "dec{<imodesuffix>}\t%0";
}
default:
gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (x86_maybe_negate_const_int (&operands[2], SImode))
- return "add{l}\t{%2, %0|%0, %2}";
+ if (x86_maybe_negate_const_int (&operands[2], <MODE>mode))
+ return "add{<imodesuffix>}\t{%2, %0|%0, %2}";
- return "sub{l}\t{%2, %0|%0, %2}";
+ return "sub{<imodesuffix>}\t{%2, %0|%0, %2}";
}
}
[(set (attr "type")
- (if_then_else (match_operand:SI 2 "incdec_operand" "")
+ (if_then_else (match_operand:<MODE> 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
@@ -6799,93 +6649,16 @@
(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
(const_string "1")
(const_string "*")))
- (set_attr "mode" "SI")])
+ (set_attr "mode" "<MODE>")])
-; See comments above addsi_4 for details.
-
-(define_insn "*addhi_4"
- [(set (reg FLAGS_REG)
- (compare
- (match_operand:HI 1 "nonimmediate_operand" "0")
- (match_operand:HI 2 "const_int_operand" "n")))
- (clobber (match_scratch:HI 0 "=rm"))]
- "ix86_match_ccmode (insn, CCGCmode)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == constm1_rtx)
- return "inc{w}\t%0";
- else
- {
- gcc_assert (operands[2] == const1_rtx);
- return "dec{w}\t%0";
- }
-
- default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (x86_maybe_negate_const_int (&operands[2], HImode))
- return "add{w}\t{%2, %0|%0, %2}";
-
- return "sub{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-; See comments above addsi_4 for details.
-
-(define_insn "*addqi_4"
- [(set (reg FLAGS_REG)
- (compare
- (match_operand:QI 1 "nonimmediate_operand" "0")
- (match_operand:QI 2 "const_int_operand" "n")))
- (clobber (match_scratch:QI 0 "=qm"))]
- "ix86_match_ccmode (insn, CCGCmode)"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255))
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == const1_rtx);
- return "dec{b}\t%0";
- }
-
- default:
- gcc_assert (rtx_equal_p (operands[0], operands[1]));
- if (x86_maybe_negate_const_int (&operands[2], QImode))
- return "add{b}\t{%2, %0|%0, %2}";
-
- return "sub{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
(define_insn "*add<mode>_5"
[(set (reg FLAGS_REG)
(compare
- (plus:SWI48
- (match_operand:SWI48 1 "nonimmediate_operand" "%0")
- (match_operand:SWI48 2 "<general_operand>" "<g>"))
+ (plus:SWI
+ (match_operand:SWI 1 "nonimmediate_operand" "%0")
+ (match_operand:SWI 2 "<general_operand>" "<g>"))
(const_int 0)))
- (clobber (match_scratch:SWI48 0 "=r"))]
+ (clobber (match_scratch:SWI 0 "=<r>"))]
"ix86_match_ccmode (insn, CCGOCmode)
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
{
@@ -6910,7 +6683,7 @@
}
}
[(set (attr "type")
- (if_then_else (match_operand:SWI48 2 "incdec_operand" "")
+ (if_then_else (match_operand:SWI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set (attr "length_immediate")
@@ -6920,81 +6693,6 @@
(const_string "*")))
(set_attr "mode" "<MODE>")])
-(define_insn "*addhi_5"
- [(set (reg FLAGS_REG)
- (compare
- (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
- (match_operand:HI 2 "general_operand" "rmn"))
- (const_int 0)))
- (clobber (match_scratch:HI 0 "=r"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{w}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx);
- return "dec{w}\t%0";
- }
-
- default:
- if (x86_maybe_negate_const_int (&operands[2], HImode))
- return "sub{w}\t{%2, %0|%0, %2}";
-
- return "add{w}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:HI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set (attr "length_immediate")
- (if_then_else
- (and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
- (const_string "1")
- (const_string "*")))
- (set_attr "mode" "HI")])
-
-(define_insn "*addqi_5"
- [(set (reg FLAGS_REG)
- (compare
- (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
- (match_operand:QI 2 "general_operand" "qmn"))
- (const_int 0)))
- (clobber (match_scratch:QI 0 "=q"))]
- "ix86_match_ccmode (insn, CCGOCmode)
- && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-{
- switch (get_attr_type (insn))
- {
- case TYPE_INCDEC:
- if (operands[2] == const1_rtx)
- return "inc{b}\t%0";
- else
- {
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
- return "dec{b}\t%0";
- }
-
- default:
- if (x86_maybe_negate_const_int (&operands[2], QImode))
- return "sub{b}\t{%2, %0|%0, %2}";
-
- return "add{b}\t{%2, %0|%0, %2}";
- }
-}
- [(set (attr "type")
- (if_then_else (match_operand:QI 2 "incdec_operand" "")
- (const_string "incdec")
- (const_string "alu")))
- (set_attr "mode" "QI")])
-
(define_insn "*addqi_ext_1_rex64"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
@@ -7015,9 +6713,7 @@
return "inc{b}\t%h0";
else
{
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
+ gcc_assert (operands[2] == constm1_rtx);
return "dec{b}\t%h0";
}
@@ -7052,9 +6748,7 @@
return "inc{b}\t%h0";
else
{
- gcc_assert (operands[2] == constm1_rtx
- || (CONST_INT_P (operands[2])
- && INTVAL (operands[2]) == 255));
+ gcc_assert (operands[2] == constm1_rtx);
return "dec{b}\t%h0";
}
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