ARM patch: Split compare_scc (PR42835)

[Richard Earnshaw]

On Fri, 2010-04-16 at 12:39 +0200, Bernd Schmidt wrote:
> This patch changes the ARM compare_scc pattern not to emit multiple
> insns.  Multiple splitters are added to handle all the alternatives.
> This has the following advantages:
>  * Reduced code duplication with thumb2.md
>  * Better instruction length estimates (occasionally leading to
>    better code)
>  * Other optimizers see exactly what's going on
> 
> The last point is the one that's important for PR42835.  Note that at
> -O2, the code generation is unchanged; crossjumping would require a new
> jump insn to be inserted.  However, at -Os, the code size optimization
> is now performed.
> 
> It took me a long time to come up with the pattern that sets flags based
> on a sub/rsbs insn; CCmodes always confuse me terribly.  However, I
> think I arrived at the correct solution: the ARM manual describes that
> for subtractions, the C flag acts as a NOT borrow flag, i.e. if A <u B,
> then after A - B, the carry flag is clear, et otherwise.
> 
> Testing in progress (arm-linux-gnueabi,
> qemu-system-armv7{arch=armv7-a/thumb,thumb,}) and looking good so far.  Ok?
> 
> This should probably be done for more patterns.

This is OK.

Note that there are several store-flag sequences that don't need
conditional execution at all.  For example:

r = (a == b)
	sub	t1, a, b
	rsbs	r, t1, #0 @(negs), C=1 => t1 == 0
	adc	r, r, t1  @ t1 + -t1 + C

On Thumb-2 that's likely to be more efficient than the moveq/movne
sequence which requires 4 insns once you include the IT insn (but
doesn't need a scratch reg).  The above sequence can also be used on
Thumb-1 (since the first and third instructions can safely clobber the
flags).

R.