[PATCH: PR target/44999] Replace "and r0, r0, #255" with uxtb in thumb2

[Carrot Wei]

On Wed, Dec 1, 2010 at 4:19 PM, Richard Earnshaw
<richard.earnshaw@buzzard.freeserve.co.uk> wrote:
> Please don't try to mix patches for different things. Firstly it makes reviewing harder.  Secondly if there's a problem found after the patch is committed the all the changes may get revered rather than just the change that caused the problem. If one part of a patch is dependent on a separate change then please say so in your submission.
>
> Now on to the details.
>
> Uxtb and uxth may generate smaller code, but on cortex-a9 they take longer to execute than AND.  So we most likely only want to do this if either optimising for size or if we can't hoist a constant out of a loop.
>
Added the condition checking.

> What's the justification for the class_likely_spilled change?  I can't immediately see why this constraint is any less likely to be true on thumb2 than on thumb1, since the contents of the class is the same (getting this wrong can cause ICEs).
>
On thumb1 only low registers can be used in normal alu instructions,
but on thumb2 nearly all registers can be used in normal alu
instructions. The register usage on thumb2 is more like that on arm
instruction set. So I think it should also have the same
class_likely_spilled behavior as arm. But anyway I removed it from the
patch.

thanks
Guozhi


ChangeLog:
2010-12-03  Wei Guozhi  <carrot@google.com>

        PR target/44999
        * config/arm/arm.md (andsi3): Revert it.
        * config/arm/thumb2.md (thumb2_zero_extendqisi2_v6): Revert it.
        (split andsi3): New split to convert and with 0xFF to uxtb.

ChangeLog:
2010-12-03  Wei Guozhi  <carrot@google.com>

        PR target/44999
        * gcc.target/arm/pr44999.c: Update it to more general.

Index: thumb2.md
===================================================================
--- thumb2.md	(revision 165462)
+++ thumb2.md	(working copy)
@@ -585,7 +585,7 @@
    (set_attr "neg_pool_range" "*,250")]
 )

-(define_insn "thumb2_zero_extendqisi2_v6"
+(define_insn "*thumb2_zero_extendqisi2_v6"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
   "TARGET_THUMB2 && arm_arch6"
@@ -1118,3 +1118,17 @@
   "
   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
   ")
+
+(define_split
+  [(set (match_operand:SI 0 "s_register_operand" "")
+	(and:SI (match_operand:SI 1 "s_register_operand" "")
+		(match_operand:SI 2 "const_int_operand" "")))]
+  "TARGET_THUMB2 && arm_arch6 && INTVAL (operands[2]) == 255
+   && (optimize_size || !arm_tune_cortex_a9)"
+  [(set (match_dup 0)
+	(zero_extend:SI (match_dup 1)))]
+  "
+  operands[1] = convert_to_mode (QImode, operands[1], 1);
+  "
+)
+
Index: arm.md
===================================================================
--- arm.md	(revision 165462)
+++ arm.md	(working copy)
@@ -2015,17 +2015,9 @@
     {
       if (GET_CODE (operands[2]) == CONST_INT)
         {
-	  if (INTVAL (operands[2]) == 255 && arm_arch6)
-	    {
-	      operands[1] = convert_to_mode (QImode, operands[1], 1);
-	      emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0],
-							 operands[1]));
-	    }
-	  else
-	    arm_split_constant (AND, SImode, NULL_RTX,
-				INTVAL (operands[2]), operands[0],
-				operands[1],
-				optimize && can_create_pseudo_p ());
+	  arm_split_constant (AND, SImode, NULL_RTX,
+			      INTVAL (operands[2]), operands[0],
+			      operands[1], optimize && can_create_pseudo_p ());

           DONE;
         }

Index: pr44999.c
===================================================================
--- pr44999.c	(revision 165462)
+++ pr44999.c	(working copy)
@@ -5,5 +5,5 @@

 int tp(int x, int y)
 {
-  return (x & 0xff) - (y & 0xffff);
+  return ((x+3) & 0xff) - (y & 0xffff);
 }