Vector misalignment

Michael Meissner meissner@linux.vnet.ibm.com
Wed Aug 18 22:46:00 GMT 2010


On Wed, Aug 18, 2010 at 06:26:50PM -0400, Michael Meissner wrote:
> On Mon, Aug 16, 2010 at 11:18:04AM -0700, Andrew Pinski wrote:
> > On Mon, Aug 16, 2010 at 11:15 AM, Artem Shinkarov
> > <artyom.shinkaroff@gmail.com> wrote:
> > > would produce no warnings, but causes a segmentation fault on intel
> > > and powerpc architecture.
> > 
> > How will it produce a seg fault on PPC (VMX) targets?  The VMX load
> > instructions don't fault but rather just use the "aligned" address.
> 
> True for VMX (altivec) target, but the VSX instruction set in power7 no longer
> ignores the bottom bits for the vector loads/stores, and so could potentially
> have an alignment failure.

Hmmm, I probably was unclear here.

The Altivec memory instructions (lvx, stvx) still ignore the bottom bits and
would never generate an alignment trap with an unaligned pointer (but it would
read the wrong data).

The VSX memory instructions (lxvw4x, lxvd2x, lxdx, lxvdsx, stxvw4x, stxvd2x,
stxdx) do not ignore the bottom bits, and can suffer an alignment trap is the
address is not aligned (alignment depends on the instruction used - the
compiler generates lxvw4x/lxvd2x depending on whether the alignment of the base
type is 8 or 4 byte aligned).  So, if you have an array of doubles or floats,
and the compiler generates a VSX memory instruction, you won't see an alignment
trap.  If you hand it a pointer that is not properly aligned for double/float,
then it may trap.

If you select VSX (-mvsx or -mcpu=power7), the compiler will generate the VSX
memory instructions instead of the Altivec memory instructions that access an
entire vector.

-- 
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA
meissner@linux.vnet.ibm.com



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