[PATCH SH2A]: Add movml instruction

[Naveen H. S]

Hi Kaz-san,

Thanks for reviewing the patch.

>> It would be far better to define correct RTLs for movml insns.  
>> Perhaps arm's implementation of ldmsi_postincN insns helps, for
>> example.

The "load_multiple" and "store_multiple" expand patterns were defined.
The RTL's were implemented that should generate movml and movmu 
instructions as per the suggestion. However, movml and movmu patterns
are very specific kind of multiple register transfers. They are 
related to push and pop patterns and hence need only R15(stack pointer 
register). Hence, these RTL's did not generate movml and movmu 
instructions.

>> Perhaps, movml peepholes like arm ldm/stm peepholes
>> instead of movml push/pop insns in the prologue/epilogue would be a
>> bit more fruitful

Peepholes are implemented to generate these multiple register transfer
patterns. However, push required register transfers from rn to r0 and 
pop required it to be from register r0 to rn. Hence, register push and 
pop sequence were modified in prologue and epilogue to meet these 
requirements. Please let me know whether the reversed sequence of push
and pop of registers would have any adverse effect on the toolchain.
  
The peepholes generated movml and movmu instruction as expected for 
sh2a target. Regressions were performed on all sh2a variants for sh-elf
toolchain and there was one failure in "gcc.dg/attr-isr.c" which checks
for push pattern. As movml instruction is generated instead of 
individual push patterns, it FAIL's. It seems to be a expected failure.

Please review the attached "sh2a_movml_movmu.patch" and let me know if
there should be any modifications in it.

ChangeLog
2010-08-13  Naveen H.S  <naveen.S@kpitcummins.com>

	* config/sh/sh.c (push_regs): Modify the sequence of register push
	to suit movml and movmu instruction requirements.
	(expand_epilogue): Likewise.
	* config/sh/sh.md: New peephole patterns to generate movml and movmu
	instructions.

Thanks & Regards,
Naveen

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