[PATCH, rtl]: Do not generate insns with mismatched REG_EQUAL mode for multiword MULT RTXes.

[Uros Bizjak]

On Wed, Aug 4, 2010 at 11:22 PM, Steven Bosscher <stevenb.gcc@gmail.com> wrote:

>> (insn 56 55 57 920501-6.c:17 (set (reg:DI 108)
>>        (reg:DI 108)) -1 (expr_list:REG_EQUAL (mult:DI (reg/v:DI 87 [ acc ])
>>            (const_int 2 [0x2]))
>>        (nil)))
>>
>> This fixes ICE on my private (unreleased) target. I didn't find the
>> testcase that would trigger on FSF targets, but the solutions should
>> be obvious from the above analysis.
>
> What happens with the REG_EQUAL note on the dummy move when the move
> is deleted? I wouldn't be surprised if this REG_EQUAL note is lost
> after the first DCE pass (which is probably a fast_dce run), because
> the dummy move looks like a noop_move_p move and these are removed
> unconditionally.

Hm, I don't know, but force_opreand in <case alg_add_factor> creates
the same dummy move at the end (so REG_NOTE attaches without problems
there):

(insn 61 60 62 920501-6.c:17 (clobber (reg:DI 112)) -1 (nil))

(insn 62 61 63 920501-6.c:17 (set (subreg:SI (reg:DI 112) 4)
        (plus:SI (subreg:SI (reg:DI 108) 4)
            (subreg:SI (reg:DI 110) 4))) -1 (nil))

(insn 63 62 64 920501-6.c:17 (set (reg:SI 113)
        (const_int 1 [0x1])) -1 (nil))

(jump_insn 64 63 65 920501-6.c:17 (set (pc)
        (if_then_else (ltu (subreg:SI (reg:DI 112) 4)
                (subreg:SI (reg:DI 108) 4))
            (label_ref 66)
            (pc))) -1 (nil))

(insn 65 64 66 920501-6.c:17 (set (reg:SI 113)
        (const_int 0 [0x0])) -1 (nil))

(code_label 66 65 67 3 "" [0 uses])

(insn 67 66 68 920501-6.c:17 (set (subreg:SI (reg:DI 112) 0)
        (plus:SI (subreg:SI (reg:DI 108) 0)
            (subreg:SI (reg:DI 110) 0))) -1 (nil))

(insn 68 67 69 920501-6.c:17 (set (reg:SI 114)
        (plus:SI (reg:SI 113)
            (subreg:SI (reg:DI 112) 0))) -1 (nil))

(insn 69 68 70 920501-6.c:17 (set (subreg:SI (reg:DI 112) 0)
        (reg:SI 114)) -1 (nil))

(insn 70 69 71 920501-6.c:17 (set (reg:DI 112)
        (reg:DI 112)) -1 (expr_list:REG_EQUAL (mult:DI (reg/v:DI 87 [ acc ])
            (const_int 10 [0xa]))
        (nil)))

Uros.