Ping: IRA-based register pressure calculation for RTL loop invariant motion

[Richard Guenther]

On Tue, Oct 20, 2009 at 4:49 AM, Vladimir Makarov <vmakarov@redhat.com> wrote:
> David Edelsohn wrote:
>>
>> On Mon, Oct 19, 2009 at 12:17 PM, Vladimir Makarov <vmakarov@redhat.com>
>> wrote:
>>
>>
>>>>
>>>> I think we could switch it on by default at -O3 for a selected group of
>>>> targets.  Itanium overall also improves with the new heuristics.  That
>>>> would
>>>> make it power and Itanium.
>>>>
>>>
>>> The patch is below.  Ok to commit?
>>>
>>>>
>>>>  Did you try restricting the heuristics to certain
>>>> register classes, like SSE registers on x86_64?
>>>>
>>>>
>>>>
>>>
>>> No, I did not try.  I am not sure it is worth to do  it.
>>>
>>>
>>> 2009-10-19  Vladimir Makarov  <vmakarov@redhat.com>
>>>
>>>  * doc/invoke.texi (fira-loop-pressure): Update default value.
>>>  * opts.c (decode_options): Remove default value setting for
>>>  flag_ira_loop_pressure.
>>>  * config/ia64/ia64.c (ia64_override_options): Set
>>>  flag_ira_loop_pressure up for -O3.
>>>  * config/rs6000/rs6000.c (rs6000_override_options): Ditto.
>>>
>>
>> Tests inside IBM do not show this IRA feature as an overall win for
>> POWER.  If we figure out and fix why artificially limiting
>> rs6000_issue_rate to 1 for the first scheduler pass still helps (and
>> it does), then this would make sense.  Until then, please do not apply
>> this patch to rs6000.
>>
>>
>
> David, I think there is some misunderstanding.  It is a different patch.
>  You are probably talking about register pressure sensitive insn scheduling
> (by the way I am still working on its tuning).  This patch is about more
> accurate register pressure calculation to decide profitability to do RTL
> loop invariant motion.  SPEC2000 and polyhedron benchmarks for power6 shows
> that this patch is a clear win.  You could test and benchmark this patch
> internally in IBM to confirm or deny my observation if you wish.

The non-powerpc pieces of the patch are ok.

Thanks,
Richard.