Ping: IRA-based register pressure calculation for RTL loop invariant motion

[Zdenek Dvorak]

Hi,

>>> +      if (i < ira_reg_class_cover_size)
>>> +	size_cost = comp_cost + 10;
>>> +      else
>>> +	size_cost = 0;
>>>     
>>
>> Including comp_cost in size_cost makes no sense (this would prevent us from
>> moving even very costly invariants out of the loop if we run out of registers).
>>
>>   
> That is exactly what I intended.  As I wrote above, I tried a lot of  
> heuristics with different parameters which decided to move loop  
> invariant depending on spill cost and loop invariant cost.  But they  
> don't  work well at least for x86/x86_64 and power6.  I have some  
> speculation for this.  x86/x86_64 is OOO processors these days.  And  
> costly invariant will be hidden because usually the invariant has a lot  
> of freedom to be executed out-of-order.  For power6, long latency is  
> hidden by insn scheduling.  It is hard to me find a processor where it  
> will be important.  Another reason for this, it is very hard to evaluate  
> accurately spill cost at this stage.  So I decided not to use  
> combination of register pressure and invariant cost in my approach.

could you please add this reasoning to the comment?  Another reason why
preventing the invariant motion does not hurt might be that all expensive
invariants were already moved out of the loop by PRE and gimple invariant
motion pass.

> +      for (i = 0; i < ira_reg_class_cover_size; i++)
> +	{
> +	  cover_class = ira_reg_class_cover[i];
> +	  if ((int) new_regs[cover_class]
> +	      + (int) regs_needed[cover_class]
> +	      + LOOP_DATA (curr_loop)->max_reg_pressure[cover_class]
> +	      + IRA_LOOP_RESERVED_REGS
> +	      - ira_available_class_regs[cover_class] > 0)
> +	    break;
> +	}

It might be clearer to write this as ... > ira_available_class_regs[cover_class] instead
of ... - ira_available_class_regs[cover_class] > 0.  Otherwise, the patch is OK.

Zdenek