[ARM] Why VFP spill slots not stack aligned?

Richard Earnshaw rearnsha@arm.com
Wed Oct 14 14:33:00 GMT 2009


On Fri, 2009-09-18 at 17:29 -0700, Doug Kwan (關振德) wrote:
> I saw a problem in which a function pushed a VFP register to an
> non-64-bit-aligned address:
> 
> 00000000 <cvt>:
>    0:   b5f0            push    {r4, r5, r6, r7, lr}
> 
>    2:   ed2d 8b02       vstmdb  sp!, {d8}
>    6:   b087            sub     sp, #28
>    8:   ec41 0b18       vmov    d8, r0, r1
> 
> The above code was generated by gcc-4.4.0.  I looked at the code in
> arm.c and there is no code to ensure that the VFP registers are
> spilled to 64-bit aligned addresses.  Is that a bug?

No.

Potentially sub-optimal in terms of performance on some implementations,
but perfectly acceptable architecturally.

R.



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