PATCH: Add LWP support for upcoming AMD Orochi processor.

[Jakub Jelinek]

On Wed, Sep 30, 2009 at 11:06:23PM -0500, Harsha Jagasia wrote:
> - Currently the code for the lwpval and lwpins instructions is
> commented out. These instructions are different from typical
> instructions in that they have no destination register
> (please see the spec). I am not sure how to repesent the patterns
> for the same and would appreciate some input.

> +;;(define_insn "lwp_lwpvalhi3"
> +;;  [(unspec [(match_operand:HI 0 "register_operand" "r")
> +;;  	   (match_operand:SI 1 "nonimmediate_operand" "rm")
> +;;	   (match_operand:HI 2 "const_int_operand" "")]
> +;;  	   UNSPEC_LWPVAL_INTRINSIC)]
> +;;  "TARGET_LWP"
> +;;  "lwpval\t{%2, %1, %0|%0, %1, %2}"
> +;;  [(set_attr "type" "lwp")
> +;;   (set_attr "mode" "HI")])

I think the easiest would be to use (unspec_volatile ... UNSPECV_LWPVAL...)
instead.  Otherwise the insn that doesn't set any register may be eliminated
as unneeded.

	Jakub