[patch committed] Fix PR target/40265

[Kaz Kojima]

Hi,

The attached patch is to fix PR target/40265 which caused
a build failure on the unified tree.  sh_expand_t_scc
generated a scc insn for SH2A which confused combine phase.
Fixed with generating it as a simple arithmetic form.
The patch is tested with bootstrap and regtested on
sh4-unknown-linux-gnu with no new failures.

Regards,
	kaz
--
2009-05-28  Kaz Kojima  <kkojima@gcc.gnu.org>

	PR target/40265
	* config/sh/sh.c (sh_expand_t_scc): Use gen_xorsi3_movrt
	instead of gen_movrt.
	* config/sh/sh.md (movrt): Remove.

diff -uprN ORIG/trunk/gcc/config/sh/sh.c trunk/gcc/config/sh/sh.c
--- ORIG/trunk/gcc/config/sh/sh.c	2009-05-25 08:19:47.000000000 +0900
+++ trunk/gcc/config/sh/sh.c	2009-05-27 07:32:14.000000000 +0900
@@ -11085,7 +11085,7 @@ sh_expand_t_scc (rtx operands[])
     emit_insn (gen_movt (result));
   else if (TARGET_SH2A && ((code == EQ && val == 0)
 			    || (code == NE && val == 1)))
-    emit_insn (gen_movrt (result));
+    emit_insn (gen_xorsi3_movrt (result));
   else if ((code == EQ && val == 0) || (code == NE && val == 1))
     {
       emit_clobber (result);
diff -uprN ORIG/trunk/gcc/config/sh/sh.md trunk/gcc/config/sh/sh.md
--- ORIG/trunk/gcc/config/sh/sh.md	2009-05-19 10:49:14.000000000 +0900
+++ trunk/gcc/config/sh/sh.md	2009-05-27 07:32:14.000000000 +0900
@@ -9109,16 +9109,6 @@ mov.l\\t1f,r0\\n\\
   "movt	%0"
   [(set_attr "type" "arith")])
 
-;; complements the T bit and stores the result in a register
-(define_insn "movrt"
-  [(set (match_operand:SI 0 "arith_reg_dest" "=r")
-        (if_then_else (eq:SI (reg:SI T_REG) (const_int 0))
-        (const_int 1)
-        (const_int 0)))]
-  "TARGET_SH2A"
-  "movrt\\t%0"
-   [(set_attr "type" "arith")])
-
 (define_expand "cstore4_media"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operator:SI 1 "sh_float_comparison_operator"