PATCH: Use optimize_insn_for_size_p instead of optimize_size

[H.J. Lu]

On Wed, May 6, 2009 at 12:29 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Wed, May 6, 2009 at 12:25 AM, H.J. Lu <hongjiu.lu@intel.com> wrote:
>
>> I think we should use optimize_insn_for_size_p instead of optimize_size.
>> Tested on Linux/Intel64. OK for trunk?
>
>> 2009-05-05  H.J. Lu  <hongjiu.lu@intel.com>
>>
>>        * config/i386/i386.md: Use optimize_insn_for_size_p instead
>
> .../i386.md (unnamed inc/dec peephole): Use ...
>
>>        of optimize_size.
>>        * config/i386/sse.md (divv8sf3): Likewise.
>>        (sqrtv8sf2): Likewise.
>
> Please note that sqrv8sf2 change is not included in attached patch.
>
> Also, it looks to me that you need to change optimize_size in
> predicates.md (incdec_operand).
>
> OK for mainline after regression testing this change on
> !TARGET_USE_INCDEC target.
>

I am checking in this updated patch. Tested with -mtune=generic, which turns off
TARGET_USE_INCDEC.

Thanks.


-- 
H.J.
---2009-05-06  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.md ((unnamed inc/dec peephole): Use
	optimize_insn_for_size_p instead
	of optimize_size.
	* config/i386/predicates.md (incdec_operand): Likewise.
	(aligned_operand): Likewise.
	* config/i386/sse.md (divv8sf3): Likewise.
	(sqrtv8sf2): Likewise.
-------------- next part --------------
2009-05-05  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.md ((unnamed inc/dec peephole): Use
	optimize_insn_for_size_p instead
	of optimize_size.
	* config/i386/predicates.md (incdec_operand): Likewise.
	(aligned_operand): Likewise.
	* config/i386/sse.md (divv8sf3): Likewise.
	(sqrtv8sf2): Likewise.

Index: gcc/config/i386/i386.md
===================================================================
--- gcc/config/i386/i386.md	(revision 147173)
+++ gcc/config/i386/i386.md	(working copy)
@@ -21230,7 +21230,7 @@
 	(match_operator 1 "compare_operator"
 	  [(match_operand 2 "register_operand" "")
 	   (match_operand 3 "const_int_operand" "")]))]
-  "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_size)
+  "(((!TARGET_FUSE_CMP_AND_BRANCH || optimize_insn_for_size_p ())
      && incdec_operand (operands[3], GET_MODE (operands[3])))
     || (!TARGET_FUSE_CMP_AND_BRANCH
 	&& INTVAL (operands[3]) == 128))
Index: gcc/config/i386/predicates.md
===================================================================
--- gcc/config/i386/predicates.md	(revision 147173)
+++ gcc/config/i386/predicates.md	(working copy)
@@ -702,7 +702,7 @@
 {
   /* On Pentium4, the inc and dec operations causes extra dependency on flag
      registers, since carry flag is not set.  */
-  if (!TARGET_USE_INCDEC && !optimize_size)
+  if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
     return 0;
   return op == const1_rtx || op == constm1_rtx;
 })
@@ -816,7 +816,7 @@
 
   /* All patterns using aligned_operand on memory operands ends up
      in promoting memory operand to 64bit and thus causing memory mismatch.  */
-  if (TARGET_MEMORY_MISMATCH_STALL && !optimize_size)
+  if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
     return 0;
 
   /* Don't even try to do any aligned optimizations with volatiles.  */
Index: gcc/config/i386/sse.md
===================================================================
--- gcc/config/i386/sse.md	(revision 147173)
+++ gcc/config/i386/sse.md	(working copy)
@@ -649,7 +649,7 @@
 {
   ix86_fixup_binary_operands_no_copy (DIV, V8SFmode, operands);
 
-  if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
+  if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
       && flag_finite_math_only && !flag_trapping_math
       && flag_unsafe_math_optimizations)
     {
@@ -800,7 +800,7 @@
 	(sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "")))]
   "TARGET_AVX"
 {
-  if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
+  if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
       && flag_finite_math_only && !flag_trapping_math
       && flag_unsafe_math_optimizations)
     {