[cond-optab] Convert mn10300
Paolo Bonzini
bonzini@gnu.org
Thu Mar 26 09:02:00 GMT 2009
Being a cc0 target, the mn10300 also has to deal with the removal of tst
instructions. This requires two small tweaks at the rtx costs.
2009-03-23 Paolo Bonzini <bonzini@gnu.org>
* config/mn10300/mn10300.c (mn10300_rtx_costs): Consider 0 and
zero_extract to be cheap in (compare (zero_extract) (const_int 0).
* config/mn10300/mn10300.md (tst): Delete.
(*tst_extqisi_am33, *tst_extqisi, *tst_exthisi_am33, *tst_exthisi):
Name these patterns and wrap RHS in a compare.
(*cmpsi): Make this pattern private. Include tst.
(*cmpsf): Make this pattern private.
(and and zero_extract cc0 set): Wrap RHS in a COMPARE.
(compare with zero peepholes): Likewise.
(bCC): Remove.
(cbranchsi4, cbranchsf4): New.
(casesi): Use cbranchsi4.
Index: gcc/config/mn10300/mn10300.c
===================================================================
--- gcc/config/mn10300/mn10300.c (branch cond-optab)
+++ gcc/config/mn10300/mn10300.c (working copy)
@@ -2022,7 +2022,7 @@ mn10300_rtx_costs (rtx x, int code, int
{
case CONST_INT:
/* Zeros are extremely cheap. */
- if (INTVAL (x) == 0 && outer_code == SET)
+ if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
*total = 0;
/* If it fits in 8 bits, then it's still relatively cheap. */
else if (INT_8_BITS (INTVAL (x)))
@@ -2051,6 +2051,12 @@ mn10300_rtx_costs (rtx x, int code, int
*total = 8;
return true;
+ case ZERO_EXTRACT:
+ /* This is cheap, we can use btst. */
+ if (outer_code == COMPARE)
+ *total = 0;
+ return false;
+
/* ??? This probably needs more work. */
case MOD:
case DIV:
Index: gcc/config/mn10300/mn10300.md
===================================================================
--- gcc/config/mn10300/mn10300.md (branch cond-optab)
+++ gcc/config/mn10300/mn10300.md (working copy)
@@ -826,34 +826,34 @@
;; TEST INSTRUCTIONS
;; ----------------------------------------------------------------------
-;; Go ahead and define tstsi so we can eliminate redundant tst insns
-;; when we start trying to optimize this port.
-(define_insn "tstsi"
- [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
- ""
- "* return output_tst (operands[0], insn);"
- [(set_attr "cc" "set_znv")])
-
-(define_insn ""
- [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a")))]
+(define_insn "*tst_extqisi_am33"
+ [(set (cc0) (compare
+ (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx,!a"))
+ (const_int 0)))]
"TARGET_AM33"
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
-(define_insn ""
- [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
+(define_insn "*tst_extqisi"
+ [(set (cc0) (compare
+ (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx"))
+ (const_int 0)))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
-(define_insn ""
- [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a")))]
+(define_insn "*tst_exthisi_am33"
+ [(set (cc0) (compare
+ (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx,!a"))
+ (const_int 0)))]
"TARGET_AM33"
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
-(define_insn ""
- [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
+(define_insn "*tst_exthisi"
+ [(set (cc0) (compare
+ (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx"))
+ (const_int 0)))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
@@ -874,17 +874,22 @@
;; possibly satisfied, so just mark the alternative with a `!', so
;; that it is not considered by reload.
-(define_insn "cmpsi"
+(define_insn "*cmpsi"
[(set (cc0)
- (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
- (match_operand:SI 1 "nonmemory_operand" "*0,daxi")))]
+ (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax,dax")
+ (match_operand:SI 1 "nonmemory_operand" "*0,I,daxi")))]
""
- "@
- btst 0,d0
- cmp %1,%0"
- [(set_attr "cc" "compare,compare")])
+ "*
+{
+ if (which_alternative == 0)
+ return \"btst 0,d0\";
+ if (which_alternative == 1)
+ return output_tst (operands[0], insn);
+ return \"cmp %1,%0\";
+}"
+ [(set_attr "cc" "compare,set_znv,compare")])
-(define_insn "cmpsf"
+(define_insn "*cmpsf"
[(set (cc0)
(compare (match_operand:SF 0 "register_operand" "f,f")
(match_operand:SF 1 "nonmemory_operand" "f,F")))]
@@ -1510,9 +1515,10 @@
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
- (match_operand 1 "const_int_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (const_int 0)))]
""
"*
{
@@ -1537,9 +1543,10 @@
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
- (match_operand 1 "const_int_operand" "")
- (match_operand 2 "const_int_operand" "")))]
+ (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" ""))
+ (const_int 0)))]
"mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
"*
{
@@ -1581,17 +1588,19 @@
[(set_attr "cc" "clobber")])
(define_insn ""
- [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
- (match_operand:SI 1 "const_int_operand" "")))]
+ [(set (cc0) (compare (and:SI (match_operand:SI 0 "register_operand" "dx")
+ (match_operand:SI 1 "const_int_operand" ""))
+ (const_int 0)))]
""
"btst %1,%0"
[(set_attr "cc" "clobber")])
(define_insn ""
[(set (cc0)
- (and:SI
- (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
- (match_operand:SI 1 "const_8bit_operand" "")))]
+ (compare (and:SI
+ (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
+ (match_operand:SI 1 "const_8bit_operand" ""))
+ (const_int 0)))]
""
"@
btst %U1,%A0
@@ -1603,97 +1612,34 @@
;; JUMP INSTRUCTIONS
;; ----------------------------------------------------------------------
-;; Conditional jump instructions
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
+(define_expand "cbranchsi4"
+ [(set (cc0)
+ (compare (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))
+ (set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator" [(cc0)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
"")
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
+(define_expand "cbranchsf4"
+ [(set (cc0)
+ (compare (match_operand:SF 1 "register_operand" "")
+ (match_operand:SF 2 "nonmemory_operand" "")))
+ (set (pc)
+ (if_then_else
+ (match_operator 0 "ordered_comparison_operator" [(cc0)
+ (const_int 0)])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
+ "TARGET_AM33_2"
"")
-(define_expand "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-(define_expand "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
+;; Conditional jump instructions
(define_insn ""
[(set (pc)
@@ -1774,11 +1720,13 @@
rtx table = gen_reg_rtx (SImode);
rtx index = gen_reg_rtx (SImode);
rtx addr = gen_reg_rtx (Pmode);
+ rtx test;
emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
emit_move_insn (index, plus_constant (operands[0], - INTVAL (operands[1])));
- emit_insn (gen_cmpsi (index, operands[2]));
- emit_jump_insn (gen_bgtu (operands[4]));
+ test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]);
+ emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4]));
+
emit_move_insn (index, gen_rtx_ASHIFT (SImode, index, const2_rtx));
emit_move_insn (addr, gen_rtx_MEM (SImode,
gen_rtx_PLUS (SImode, table, index)));
@@ -2518,7 +2466,8 @@
;; This will work on the mn10200 because we can check the ZX flag
;; if the comparison is in HImode.
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "dx")
+ (const_int 0)))
(set (pc) (if_then_else (ge (cc0) (const_int 0))
(match_operand 1 "" "")
(pc)))]
@@ -2527,7 +2476,8 @@
[(set_attr "cc" "clobber")])
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "dx")
+ (const_int 0)))
(set (pc) (if_then_else (lt (cc0) (const_int 0))
(match_operand 1 "" "")
(pc)))]
@@ -2536,7 +2486,8 @@
[(set_attr "cc" "clobber")])
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "dx")
+ (const_int 0)))
(set (pc) (if_then_else (ge (cc0) (const_int 0))
(pc)
(match_operand 1 "" "")))]
@@ -2545,7 +2496,8 @@
[(set_attr "cc" "clobber")])
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
+ [(set (cc0) (compare (match_operand:SI 0 "register_operand" "dx")
+ (const_int 0)))
(set (pc) (if_then_else (lt (cc0) (const_int 0))
(pc)
(match_operand 1 "" "")))]
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