[PATCH] MIPS: Fix PR target/39079, __builtin___clear_cache() broken on SMP ISA_HAS_SYNCI systems.

[David Daney]

 From the bug:

   We expand __builtin___clear_cache() to a 'synci' instruction on
   ISA_HAS_SYNCI systems, which invalidates the icache only on the
   local CPU.

   On an SMP system, the caches on all CPUs should be invalidated.  To
   achieve this we need to drop back to the old way of doing things by
   using the cache flush system call.


To fix this, I added a new command line option (-msynci/-mno-synci) that 
enables and disables the generation of the synci instruction for 
clearing the icache.  The default is to disable synci, but the default 
can be overridden at configure time with the --with-synci option.

Tested on mips64-linux configured with --with-arch=octeon.

OK to commit?

gcc/
2009-06-29  David Daney  <ddaney@caviumnetworks.com>

	PR target/39079
	* config.gcc (supported_defaults): Add synci.
	(with_synci): Add validation.
	(all_defaults): Add synci.
	* config/mips/mips.md (clear_cache): Use TARGET_SYNCI instead of
	ISA_HAS_SYNCI.
	(synci): Same.
	* config/mips/mips.opt (msynci): New option.
	* config/mips/mips.c (mips_override_options): Warn on use of
	-msynci for targets that do now support it.
	* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
	msynci.
	* gcc/doc/invoke.texi (-msynci): Document the new option.
	* doc/install.texi (--with-synci): Document the new option.

gcc/testsuite/
2009-06-29  David Daney  <ddaney@caviumnetworks.com>

	PR target/39079
	* testsuite/gcc.target/mips/mips.exp: Make -msynci a known option.
	* gcc.target/mips/clear-cache-1.c (dg-options): Add -msynci.
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