[power7-meissner] Vectorize simple math builtins

[Michael Meissner]

On Tue, Jul 14, 2009 at 01:19:55AM +0200, Paolo Bonzini wrote:
> On 07/13/2009 11:28 PM, Michael Meissner wrote:
> >+    case BUILT_IN_COPYSIGNF:
> >+      if (VECTOR_UNIT_VSX_P (V4SFmode)
> >+	&&  out_mode == SFmode&&  out_n == 4
> >+	&&  in_mode == SFmode&&  in_n == 4)
> >+	return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
> >+      break;
> 
> Since the implementation for Altivec should be as simple as this:
> 
> 	vspltisw	v1,-1	; v1 = (0xFFFFFFFF, ...)
> 	vxor	v2,v3,v4
> 	vslw	v1,v1,v1	; v1 = v1 << 31 = (0x80000000, ...)
> 	vand	v1,v1,v2	; v1 != 0 if sign bits of v3/v4 differ
> 	vxor	v1,v1,v3	; v1 = v3 with v4's sign bits
> 
> Maybe it's worthwhile making it available for Altivec too.
> 
> Paolo

Yep.  Good idea.  I'll put it on the queue.

-- 
Michael Meissner, IBM
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