[PATCH] s390: z10 scheduler fixes part 3/4

Andreas Krebbel krebbel@linux.vnet.ibm.com
Thu Jan 29 08:28:00 GMT 2009


Hi Wolfgang,

splitting up the insn is ok with me. It indeed makes it somewhat more 
readable.

But I don't think the remaining insv_h* pattern makes sense for 32 bit 
anymore and will not be matched anyway:

! (define_insn "*insv_h<mode>_reg_extimm"
     [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
   			(const_int 32)
   			(match_operand 1 "const_int_operand" "n"))
   	(match_operand:P 2 "const_int_operand" "n"))]
     "TARGET_EXTIMM
!    && BITS_PER_WORD - INTVAL (operands[1]) == 64"
!   "iihf\t%0,%o2"
     [(set_attr "op_type" "RIL")
      (set_attr "z10prop" "z10_fwd_E1")])


I think it better should look like this:

(define_insn "*insv_hdi_reg_extimm"
   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
			(const_int 32)
			(const_int 0))
	(match_operand:P 2 "const_int_operand" "n"))]
   "TARGET_EXTIMM"
   "iihf\t%0,%o2"
   [(set_attr "op_type" "RIL")
    (set_attr "z10prop" "z10_fwd_E1")])

Bye,

-Andreas-



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