[PATCH,committed] fix ICE caused by lax rs6000_legitimize_address

Nathan Froyd froydnj@codesourcery.com
Wed Jan 7 23:38:00 GMT 2009


I've committed the patch submitted here:

  http://gcc.gnu.org/ml/gcc-patches/2008-11/msg00401.html

as modified by Alan here:

  http://gcc.gnu.org/ml/gcc-patches/2008-11/msg00571.html

David OK'd the patch in the original thread and re-OK'd it after the
month-and-a-half time lapse on IRC today.

-Nathan

gcc/

	* config/rs6000/rs6000.c (rs6000_legitimize_address): Check for
	non-word-aligned REG+CONST addressing.

gcc/testsuite/

	* gcc.c-torture/compile/20090107-1.c: New test.

Index: gcc/ChangeLog
===================================================================
Index: gcc/testsuite/gcc.c-torture/compile/20090107-1.c
===================================================================
--- gcc/testsuite/gcc.c-torture/compile/20090107-1.c	(revision 0)
+++ gcc/testsuite/gcc.c-torture/compile/20090107-1.c	(revision 0)
@@ -0,0 +1,25 @@
+/* Verify that we don't ICE by forming invalid addresses for unaligned
+   doubleword loads (originally for PPC64).  */
+
+struct a
+{
+ unsigned int x;
+ unsigned short y;
+} __attribute__((packed));
+
+struct b {
+ struct a rep;
+ unsigned long long seq;
+} __attribute__((packed));
+
+struct c {
+ int x;
+ struct a a[5460];
+ struct b b;
+};
+
+extern void use_ull(unsigned long long);
+extern void f(struct c *i) {
+  use_ull(i->b.seq);
+  return;
+}
Index: gcc/testsuite/ChangeLog
===================================================================
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 143170)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -3804,7 +3804,10 @@ rs6000_legitimize_address (rtx x, rtx ol
       && GET_CODE (XEXP (x, 0)) == REG
       && GET_CODE (XEXP (x, 1)) == CONST_INT
       && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
-      && !(SPE_VECTOR_MODE (mode)
+      && !((TARGET_POWERPC64
+	    && (mode == DImode || mode == TImode)
+	    && (INTVAL (XEXP (x, 1)) & 3) != 0)
+	   || SPE_VECTOR_MODE (mode)
 	   || ALTIVEC_VECTOR_MODE (mode)
 	   || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
 				      || mode == DImode || mode == DDmode



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