PATCH: Update classification of aggregates with __m256 ([AVX]: Update x86-64 psABI for aggregates with __m256)

[H.J. Lu]

On Wed, Feb 11, 2009 at 10:16 AM, Harsha Jagasia <harsha.jagasia@amd.com> wrote:
>> -------------
>> @@ -5331,14 +5352,22 @@ construct_container (enum machine_mode m
>>           break;
>>         case X86_64_SSE_CLASS:
>>           if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
>> -           tmpmode = TImode;
>> +           {
>> +             if (regclass[i + 2] == X86_64_SSEUP_CLASS
>> +                 || regclass[i + 3] == X86_64_SSEUP_CLASS)
>> +               tmpmode = OImode;
>> +             else
>> +               tmpmode = TImode;
>> +           }
>>
>
>
> I would think a check for n is needed here. If n is 2, regclass[i + 2] and regclass[i + 3] would not be valid, right?
>

This patch rewrites processing BLKmode with X86_64_SSE_CLASS.
OK for trunk if there is no regression on Linux/x86-64?

Thanks.


-- 
H.J.
---
2009-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (construct_container): Rewrite processing
	BLKmode with X86_64_SSE_CLASS.
-------------- next part --------------
2009-02-11  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (construct_container): Rewrite processing
	BLKmode with X86_64_SSE_CLASS.

--- gcc/config/i386/i386.c.m256	2009-02-10 14:27:17.000000000 -0800
+++ gcc/config/i386/i386.c	2009-02-11 11:33:54.000000000 -0800
@@ -5328,6 +5328,8 @@ construct_container (enum machine_mode m
   /* Otherwise figure out the entries of the PARALLEL.  */
   for (i = 0; i < n; i++)
     {
+      int pos;
+
       switch (regclass[i])
         {
 	  case X86_64_NO_CLASS:
@@ -5364,24 +5366,36 @@ construct_container (enum machine_mode m
 	    sse_regno++;
 	    break;
 	  case X86_64_SSE_CLASS:
-	    if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
+	    pos = i;
+	    switch (n)
 	      {
-		if (regclass[i + 2] == X86_64_SSEUP_CLASS
-		    || regclass[i + 3] == X86_64_SSEUP_CLASS)
-		  tmpmode = OImode;
+	      case 1:
+		tmpmode = DImode;
+		break;
+	      case 2:
+		if (i == 0 && regclass[1] == X86_64_SSEUP_CLASS)
+		  {
+		    tmpmode = TImode;
+		    i++;
+		  }
 		else
-		  tmpmode = TImode;
+		  tmpmode = DImode;
+		break;
+	      case 4:
+		gcc_assert (i == 0
+			    && regclass[1] == X86_64_SSEUP_CLASS
+			    && regclass[2] == X86_64_SSEUP_CLASS
+			    && regclass[3] == X86_64_SSEUP_CLASS);
+		tmpmode = OImode;
+		i += 3;
+		break;
+	      default:
+		gcc_unreachable ();
 	      }
-	    else
-	      tmpmode = DImode;
 	    exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
 					       gen_rtx_REG (tmpmode,
 							    SSE_REGNO (sse_regno)),
-					       GEN_INT (i*8));
-	    if (tmpmode == OImode)
-	      i += 3;
-	    else if (tmpmode == TImode)
-	      i++;
+					       GEN_INT (pos*8));
 	    sse_regno++;
 	    break;
 	  default: