4.5 release notes for target-specific improvements
Joseph S. Myers
joseph@codesourcery.com
Tue Dec 8 17:50:00 GMT 2009
I've applied this patch to add 4.5 release notes for various
target-specific improvements for ARM, M68K/ColdFire, MIPS and PowerPC.
I'm sure there are more such improvements, both for these targets and for
other targets; target maintainers need to look at changes for their
targets and add release notes as appropriate.
Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.5/changes.html,v
retrieving revision 1.54
diff -u -r1.54 changes.html
--- changes.html 8 Dec 2009 16:59:37 -0000 1.54
+++ changes.html 8 Dec 2009 17:35:56 -0000
@@ -416,6 +416,25 @@
<li>Full cross-toolchain support now available with GNU Binutils</li>
</ul>
+<h3>ARM</h3>
+ <ul>
+ <li>GCC now supports the Cortex-M0 and Cortex-A5 processors.</li>
+ <li>GCC now supports the ARM v7E-M architecture.</li>
+ <li>GCC now supports VFPv4-based FPUs and FPUs with
+ single-precision-only VFP.</li>
+ <li>GCC has many improvements to optimization for other ARM
+ processors, including scheduling support for the integer pipeline
+ on Cortex-A9.</li>
+ <li>GCC now supports the IEEE 754-2008 half-precision
+ floating-point type, and a variant ARM-specific half-precision
+ type. This type is specified using <code>__fp16</code>, with the
+ layout determined by <code>-mfp16-format</code>. With
+ appropriate <code>-mfpu</code> options, the Cortex-A9 and VFPv4
+ half-precision instructions will be used.</li>
+ <li>GCC now supports the variant of AAPCS that uses VFP registers
+ for parameter passing and return values.</li>
+ </ul>
+
<h3>AVR</h3>
<ul>
<li>The <code>-mno-tablejump</code> option has been removed because it
@@ -441,12 +460,28 @@
<code>-march=atom</code> and <code>-mtune=atom</code> options.</li>
</ul>
+<h3>M68K/ColdFire</h3>
+ <ul>
+ <li>GCC now supports ColdFire 51xx, 5221x, 5225x, 52274, 52277,
+ 5301x and 5441x devices.</li>
+ <li>GCC now supports thread-local storage (TLS) on M68K and
+ ColdFire processors.</li>
+ </ul>
+
<h3 id="mep">MeP</h3>
<p>Support has been added for the Toshiba Media embedded Processor (MeP, or
mep-elf) embedded target.</p>
<h3>MIPS</h3>
+ <ul>
+ <li>GCC now supports MIPS 1004K processors.</li>
+ <li>GCC can now be configured with
+ options <code>--with-arch-32</code>, <code>--with-arch-64</code>,
+ <code>--with-tune-32</code> and <code>--with-tune-64</code> to
+ control the default optimization separately for 32-bit and 64-bit
+ modes.</li>
+ </ul>
<h3 id="picochip">picochip</h3>
@@ -464,14 +499,20 @@
<li>Support for the 476 processor is now available through the
<code>-mcpu={476,476fp}</code> and <code>-mtune={476,476fp}</code>
options.</li>
+ <li>Support for the e500mc64 processor is now available through
+ the <code>-mcpu=e500mc64</code>
+ and <code>-mtune=e500mc64</code> options.</li>
+ <li>GCC can now be configured with
+ options <code>--with-cpu-32</code>, <code>--with-cpu-64</code>,
+ <code>--with-tune-32</code> and <code>--with-tune-64</code> to
+ control the default optimization separately for 32-bit and 64-bit
+ modes.</li>
</ul>
<h3 id="rx">RX</h3>
<p>Support has been added for the Renesas RX Processor (rx-elf) target.</p>
-<h3>MIPS</h3>
-
<h2>Documentation improvements</h2>
<h2>Other significant improvements</h2>
--
Joseph S. Myers
joseph@codesourcery.com
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