[Patch ARM] Fix ICE in neon shift patterns with constant ints.

[Ramana Radhakrishnan]

Hi, 

The vshl<vmode>, vlshr<vmode> and vashr<vmode>  patterns have not been
defined for Neon and this causes an ICE  in a well known embedded
benchmark using the options -O3 -mcpu=cortex-a8 -mfpu=neon
-mfloat-abi=softfp .  The neon backend has ashl<vmode>,lshr<vmode>* and 
ashr<vmode> patterns already defined. I've renamed them here to the
corresponding vector shift patterns and that fixes the ICE. 

I've built and tested a cross toolchain for arm-none-eabi with cpu =
cortex-a8, fpu=neon and float-abi=softfp on qemu.

Ok for trunk ?

cheers
Ramana

2009-08-23  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

        * config/arm/neon.md (vashl<mode>3): Rename from ashl<mode>3.
        (vashr<mode>3): Rename from ashr<mode>3.
        (vlshr<mode>3): Rename from lshr<mode>3.


-- 
Ramana Radhakrishnan
GNU Tools
ARM Ltd.
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