[PATCH, i386]: Add support for CPUID 4 in driver-i386.c

[Uros Bizjak]

Hello!

This patch is loosely based on Andi's patch to use CPUID function 4 to 
describe Intel caches. In addition to parsing CPUID function 4 values, 
attached patch updates CPUID 2 table to the latest known CPUID 
documentation, it fixes Xeon MP CPUID fn 2 problems and handles number 
of times to execute CPUID fn 2 instruction to obtain complete cache 
hierarchy description.

In addition, struct cache_desc is introduced to pass cache descriptors 
around.

2008-10-11  Uros Bizjak  <ubizjak@gmail.com>
        Andi Kleen  <ak@linux.intel.com>

    * config/i386/cpuid.h (__cpuid_count): New defines.
    * config/i386/driver-i386.c (struct cache_desc): New structure.
    (describe_cache): Use struct cache_desc to pass cache descriptions.
    (detect_l2_cache): Ditto. Rename from decode_l2_cache.
    (detect_caches_amd): Use struct cache_desc to describe caches.
    (decode_caches_intel): Use struct cache_desc to pass cache
    descriptions.  Update descriptions to match latest (rev -032,
    December 2007) CPUID documentation.  Do not check valid bit here.
    Check for Xeon MP value 0x49 problems.
    (detect_caches_cpuid2): New function, split from detect_caches_intel.
    Check valid bit before calling decode_caches_intel.  Detect number
    of times to repeat CPUID instruction.
    (detect_caches_cpuid4): New function.
    (detect_caches_intel): Depending on max_level, call
    detect_caches_cpuid2 or detect_caches_cpuid4.  Call detect_l2_cache
    only when other methods fail to provide valid L2 cache description.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu 
{,-m32}. Also, it was checked on a couple of targets if it provides 
correct cache information to the compiler. Patch is committed to SVN.

Uros.
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