Support Xilinx PowerPC single-precision FPU

[David Edelsohn]

Michael,

Your change to fix_truncsfsi2 references gen_xil_fix_truncsfsi2,
but no xil_fix_truncsfsi2 pattern is defined in your patches.

The build succeeds only because you added
TARGET_XILINX_FPU to the final condition of the pattern, which
always is false for the rest of us, so GCC's gen programs never
emit the pattern.

But this raises another issue that your new condition changes
the behavior for processors with SPE instruction -- FP in GPRs.
The original condition was

  "TARGET_HARD_FLOAT && !TARGET_FPRS"

and now you have limited it to Xilinx, breaking the other
processors.

David

@@ -5826,10 +5857,23 @@
   "")

 (define_expand "fix_truncsfsi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "")
-       (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
-  "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
-  "")
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+                 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))
+            (clobber (match_dup 2))
+            (clobber (match_dup 3))
+            (clobber (match_dup 4))])]
+  "TARGET_HARD_FLOAT && ! TARGET_DOUBLE_FLOAT && TARGET_FPRS
+   && TARGET_SINGLE_FLOAT && TARGET_XILINX_FPU"
+  "
+  if (TARGET_XILINX_FPU)
+    {
+      operands[2] = gen_reg_rtx (SFmode);
+      operands[3] = assign_stack_temp (SFmode, GET_MODE_SIZE (SFmode), 0);
+      operands[4] = gen_rtx_MEM (SImode, XEXP (operands[3], 0));
+      emit_insn (gen_xil_fix_truncsfsi2(operands[0], operands[1], operands[2],
operands[3], operands[4]));
+      DONE;
+    }
+")