[PATCH]: GCC Scheduler support for R10000 on MIPS

[Richard Sandiford]

Kumba <kumba@gentoo.org> writes:
>> Let me know if you have svn write access.  I'll apply the patch
>> for you if not.
>
> Nope, don't have SVN write access.  This is my first gcc patch pretty much.

The copyright assignment has now gone through, so I went ahead
and applied the patch[*].  Thanks for the contribution, and for
your patience.  And thanks to Gerald for once again helping me
with the copyright stuff.

  [*] I removed the unused TARGET_MIPS10000 and TUNE_MIPS10000 macros
      though.  We generally only add those macros when they're needed
      for something.

I applied the following patch to the GCC 4.4 release notes.

Richard


Index: htdocs/gcc-4.4/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.4/changes.html,v
retrieving revision 1.34
diff -u -p -r1.34 changes.html
--- htdocs/gcc-4.4/changes.html	6 Oct 2008 18:58:44 -0000	1.34
+++ htdocs/gcc-4.4/changes.html	6 Oct 2008 19:43:50 -0000
@@ -345,6 +345,10 @@
         instead of relying on a <code>libgcc</code> function.</li>
     <li>Native GNU/Linux toolchains now support <code>-march=native</code>
         and <code>-mtune=native</code>, which select the host processor.</li>
+    <li>GCC now supports the R10K, R12K, R14K and R16K processors.  The
+        canonical <code>-march=</code> and <code>-mtune=</code> names for
+        these processors are <code>r10000</code>, <code>r12000</code>,
+        <code>r14000</code> and <code>r16000</code> respectively.</li>
     <li>GCC can now work around the side effects of speculative execution
         on R10K processors.  Please see the documentation of the
         <code>-mr10k-cache-barrier</code> option for details.</li>