PATCH: Optimize integer vector concatenate for SSE4

[Uros Bizjak]

H.J. Lu wrote:

> This patch optimizes integer vector concatenate for SSE4. I
> also renamed vector concatenate patterns to be consistent
> with other vector patterns. OK for trunk?
>
>  
> +(define_insn "*vec_concatv2si_sse4_1"
> +  [(set (match_operand:V2SI 0 "register_operand" "=x,x")
> +	(vec_concat:V2SI
> +	  (match_operand:SI 1 "register_operand" "0,rm")
>   

nonimmediate_operand

> +	  (match_operand:SI 2 "nonimmediate_operand" "rm,0")))]
> +  "TARGET_SSE4_1"
> +  "@
> +  pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
> +  pinsrd\t{$0x0, %2, %0|%0, %2, 0x0}"
> +  [(set_attr "type" "sselog")
> +   (set_attr "mode" "TI")])
>   

Please check if  insn pattern with "ix86_binary_operator_ok (...)" insn 
constraint is needed to prevent combiner from combining mem/mem input 
operands.  Eventually, expander with "x86_fixup_binary_operands_no_copy 
(UNKNOWN, SImode, operands)" is needed to fix mem/mem operands 
expansion. Looking at existing vec_concat_* patterns, I think that we 
can trust reload to fix mem/mem operands for us, so IMO no fixups or 
extra constraints are needed.

> +(define_insn "*vec_concatv2di_rex64_sse4_1"
> +  [(set (match_operand:V2DI 0 "register_operand" "=x,x")
> +	(vec_concat:V2DI
> +	  (match_operand:DI 1 "register_operand" "0,rm")
>   

nonimmediate_operand

> +	  (match_operand:DI 2 "nonimmediate_operand" "rm,0")))]
> +  "TARGET_64BIT && TARGET_SSE4_1"
> +  "@
> +  pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
> +  pinsrq\t{$0x0, %2, %0|%0, %2, 0x0}"
> +  [(set_attr "type" "sselog")
> +   (set_attr "mode" "TI")])
>   

Please change operand[1] to nomimmediate_operand in both cases.
The patch is OK for mainline with this change.

Thanks,
Uros.