[RFC PATCH, i386]: Generate bit test (bt) instructions

[Uros Bizjak]

On Tue, Jun 10, 2008 at 4:13 AM, rajagopal, dwarak
<dwarak.rajagopal@amd.com> wrote:

> This optimization might be advantageous on AMD platforms as well, though
> we haven't tested this patch on an AMD platform yet (I'll test this on a
> Barcelona machine within a couple of days). According to the AMD
> optimization guide for AMDFAM10 (aka Barcelona) and k8,
> register/register BT is a DirectPath single cycle instruction (the
> memory version is slower as it is VectorPath instruction). This can also
> be enabled for generic given that it is fast for both AMD and Intel
> current shipping systems.
>
> This should also be emitted for -Os optimizations since it eliminates
> the move instruction to load 1.

I agree that this optimization should be enabled for both, -Os and
generic targets.

This is what has been committed to SVN:

2008-06-10  Uros Bizjak  <ubizjak@gmail.com>

	PR target/36473
	* config/i386/i386.c (ix86_tune_features) [TUNE_USE_BT]:
	Add m_CORE2 and m_GENERIC.
	* config/i386/predicates.md (bt_comparison_operator): New predicate.
	* config/i386/i386.md (*btdi_rex64): New instruction pattern.
	(*btsi): Ditto.
	(*jcc_btdi_rex64): New instruction and split pattern.
	(*jcc_btsi): Ditto.
	(*jcc_btsi_1): Ditto.
	(*btsq): Fix Intel asm dialect operand order.
	(*btrq): Ditto.
	(*btcq): Ditto.

testsuite/ChangeLog:

2008-06-10  Uros Bizjak  <ubizjak@gmail.com>

	PR target/36473
	* testsuite/gcc.target/i386/bt-1.c: New test.
	* testsuite/gcc.target/i386/bt-2.c: Ditto.

Attached patch was re-tested on i686-pc-linux-gnu and x86_64-pc-linux-gnu.

Uros.
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