[MIPS] Limit lwxc1 et al on MIPS64

[Daniel Jacobowitz]

The lwxc1 (and ldxc1, swxc1, sdxc1) instructions are imlemented on
MIPS32r2 regardless of the processor mode.  On earlier ISAs, including
MIPS64 (not r2), they are only available in 64-bit mode.

This shows up with a mips-linux compiler using -mcpu=sb1, which
selects a MIPS64 processor but the o32 ABI.  The kernel might be
32-bit, and even if it's 64-bit it runs applications in 32-bit mode
(PR bit clear, IIRC).

I think it's reasonable to check the ABI before using these
instructions on pre-MIPS32r2 processors.  Dinar tested the attached
patch on mips-elf and mipsisa64-elf, and we've used it on mips64-linux
as well.  OK to commit?

-- 
Daniel Jacobowitz
CodeSourcery

2008-06-05  Dinar Temirbulatov  <dtemirbulatov@ru.mvista.com>
	    Daniel Jacobowitz  <dan@codesourcery.com>

	* mips.md (*<ANYF:loadx>_<P:mode>, *<ANYF:storex>_<P:mode>): Check
	ISA_HAS_FP4_LOADSTORE.
	* mips.h (ISA_HAS_FP4_LOADSTORE): Define.

Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	(revision 134991)
+++ gcc/config/mips/mips.md	(working copy)
@@ -3738,7 +3738,7 @@
   [(set (match_operand:ANYF 0 "register_operand" "=f")
 	(mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
 			  (match_operand:P 2 "register_operand" "d"))))]
-  "ISA_HAS_FP4"
+  "ISA_HAS_FP4_LOADSTORE"
   "<ANYF:loadx>\t%0,%1(%2)"
   [(set_attr "type" "fpidxload")
    (set_attr "mode" "<ANYF:UNITMODE>")])
@@ -3747,7 +3747,7 @@
   [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
 			  (match_operand:P 2 "register_operand" "d")))
 	(match_operand:ANYF 0 "register_operand" "f"))]
-  "ISA_HAS_FP4"
+  "ISA_HAS_FP4_LOADSTORE"
   "<ANYF:storex>\t%0,%1(%2)"
   [(set_attr "type" "fpidxstore")
    (set_attr "mode" "<ANYF:UNITMODE>")])
Index: gcc/config/mips/mips.h
===================================================================
--- gcc/config/mips/mips.h	(revision 134991)
+++ gcc/config/mips/mips.h	(working copy)
@@ -753,6 +753,12 @@ enum mips_code_readable_setting {
 				  || ISA_MIPS64)			\
 				 && !TARGET_MIPS16)
 
+/* Indexed load and store float instructions are only available in
+   64-bit mode on MIPS64; they are available in 32-bit mode on MIPS32r2
+   and MIPS64r2.  */
+#define ISA_HAS_FP4_LOADSTORE	(ISA_HAS_FP4				\
+				 && (ABI_NEEDS_64BIT_REGS || ISA_MIPS32R2))
+
 /* ISA has paired-single instructions.  */
 #define ISA_HAS_PAIRED_SINGLE	(ISA_MIPS32R2 || ISA_MIPS64)