A new gimple pass (LRS: live range shrinking) to reduce register pressure

[Andrew Pinski]

Hi,
  I noticed that you walk the trees in normalize_gimple_stmt to get
the uses, but that information is already provided by using
FOR_EACH_SSA_USE_OPERAND, this information is kept up todate too and
it works on both PHIs and normal statements.  The defines information
is also provided by FOR_EACH_SSA_DEF_OPERAND.  Also some statements
might have more than one definition (I am thinking of asms).

What happens if there is only one register class, like on the SPU.

get_nm_reg_class is going to return wrong results if you have a vector
int and a vector float.

I think it is better to use actual register classes and a target
hook/macro to find the preferred register class for the mode, rather
than the default grp/frp register class which you have, this will
allow for the issue I am talking about with dealing with targets like
SPU and targets which different register classes for vectors than from
the integer and float registers.

Thanks,
Andrew Pinski