[PATCH] PR 38201: -mfma/-mavx and -msse5/-msse4a don't work together

Michael Meissner meissner@linux.vnet.ibm.com
Wed Dec 10 01:39:00 GMT 2008

On Tue, Dec 09, 2008 at 02:48:19PM -0800, H.J. Lu wrote:
> On Tue, Dec 9, 2008 at 2:20 PM, Andrew Pinski <pinskia@gmail.com> wrote:
> > On Tue, Dec 9, 2008 at 1:43 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> >> Here is the updated patch with missing new testcases as well as
> >> new testcases for "-march=XXX -mavx". When there is a future
> >> processor which supports AVX and SSE4a/SSE5, we can
> >> update x86 backend to support it properly. Tested on Linux/ia32
> >> and Linux/Intel64.  OK for trunk?
> >
> > You still have not explained why you want this patch.  I still say we
> If we allow "-mfma -msse5", which Fused Multiple and Add instruction
> should gcc generate,  Intel FMA or AMD SSE5?

Pick one, such as the Intel FMA.

> > should allow the user to "hang themselves" here and not say they are
> It may cause unnecessary bug reports.

I don't see it that way.  It is equivalent to doing -msse4 and having the
program fail on a machine without the SSE4 instruction set.

When I was at AMD, I often times did what if type studies of enabling both
instruction sets (SSE4 and SSE5 when I was there).  I wouldn't be surprised if
somebdoy at Intel also did the same thing for the AMD instruction sets.  And
VIA seems to be coming back, maybe they want to produce a chip with both
instruction sets.  People doing these types of tests often aren't the compiler
developers.  In addition, perhaps some grad. student is looking at it in terms
of running programs in a simulator.

> > not compatible as who knows what the future processors will be like
> > and what a simulator supports.
> >
> As I said before, if there is such a processor in the future, gcc
> should be updated to properly support it. We shouldn't use the
> "ancient" gcc on such processor.

The problem is it can be a two - three year slog to get things into the next
release of GCC (new processors are not allowed in patch releases), and then
once it is in GCC, getting it into the distributions, and from there to the

Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA

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