PING: PATCH: PR rtl-optimization/38272:

H.J. Lu hjl.tools@gmail.com
Sat Dec 6 01:03:00 GMT 2008


On Fri, Dec 5, 2008 at 4:24 PM, Vladimir Makarov <vmakarov@redhat.com> wrote:
> H.J. Lu wrote:
>>
>> On Fri, Dec 5, 2008 at 1:31 PM, Ian Lance Taylor <iant@google.com> wrote:
>>
>>>
>>> "H.J. Lu" <hjl.tools@gmail.com> writes:
>>>
>>>
>>>>
>>>> IRA exposed a latent reload bug where do_input_reload use a register
>>>> spill for a memory input and the spilled register is diferent from
>>>> the register to be reloaded into. It generates wrong code.  A patch is
>>>> posted at:
>>>>
>>>> http://gcc.gnu.org/ml/gcc-patches/2008-11/msg01463.html
>>>>
>>>> Is that OK for mainline?
>>>>
>>>
>>> I don't see that that conditional serves any purpose any more.  I
>>> would try simply deleting this block of code entirely:
>>>
>>>  /* When inheriting a wider reload, we have a MEM in rl->in,
>>>    e.g. inheriting a SImode output reload for
>>>    (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10)))  */
>>>  if (optimize && reload_inherited[j] && rl->in
>>>     && MEM_P (rl->in)
>>>     && MEM_P (rl->in_reg)
>>>     && reload_spill_index[j] >= 0
>>>     && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
>>>   rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
>>>
>>> It would certainly be interesting to hear what it does affect.  That
>>> code was introduced before we had any equivalent of the reg_rtx field
>>> in struct reload.
>>>
>>>
>>
>> I will remove this block of code on ira-merge branch. I will run
>> SPEC CPU 2K/2006 on Linux/ia32 and Linux/Intel64 to
>> see if there are any performance impacts.
>>
>>
>
> I am sorry, HJ.  I think you missed Bernd's patch.
>
> http://gcc.gnu.org/ml/gcc-patches/2008-12/msg00172.html
>
> If it works, it is more right solution imho and Bernd's patch is
> automatically approved because Bernd is a reload maintainer.
>

Yes, it works on the testcase. I will do a full regression test.
I will check it in if it passes.

Thanks.


-- 
H.J.



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