[AVX] Don't generate 2 insns for *avx_mov<mode>_internal

[H.J. Lu]

I used 2 insns to load all 1s into AVX register w/o using memory for
the *avx_mov<mode>_internal pattern. We should expand it into a
sequence of 2 patterns.  I checked this patch into AVX branch to
remove 2 insns for *avx_mov<mode>_internal.  We will get an ICE if we
are trying to do it. I will fix it properly then.

Thanks.


H.J.
-----
Index: ChangeLog.avx
===================================================================
--- ChangeLog.avx	(revision 139123)
+++ ChangeLog.avx	(working copy)
@@ -1,3 +1,15 @@
+2008-08-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (standard_sse_mode_p): Return 2 for 256bit
+	AVX modes.
+	(standard_sse_constant_p): Return -2 for all 1s if SSE2 isn't
+	enabled.  For all 1s in 256bit AVX modes, return 3 if AVX is
+	enabled, otherwise return -3.
+	(standard_sse_constant_opcode): Remove MODE_V8SF, MODE_V4DF
+	and MODE_OI.
+
+	* config/i386/sse.md (*avx_mov<mode>_internal): Remove FIXME.
+
 2008-08-14  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/37101
Index: config/i386/sse.md
===================================================================
--- config/i386/sse.md	(revision 139123)
+++ config/i386/sse.md	(working copy)
@@ -148,9 +148,6 @@
   DONE;
 })
 
-;; FIXME: If standard_sse_constant_opcode returns 2 instructions to
-;; fill 256bit AVX register with all 1s, instruction length will be
-;; incorrect.
 (define_insn "*avx_mov<mode>_internal"
   [(set (match_operand:AVXMODE 0 "nonimmediate_operand" "=x,x ,m")
 	(match_operand:AVXMODE 1 "nonimmediate_or_sse_const_operand"  "C ,xm,x"))]
Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 139123)
+++ config/i386/i386.c	(working copy)
@@ -6938,7 +6938,9 @@ standard_80387_constant_rtx (int idx)
 				       XFmode);
 }
 
-/* Return 1 if mode is a valid mode for sse.  */
+/* Return 1 if mode is a valid mode for sse and return 2 if mode is a
+   valid mode for AVX.  */
+
 static int
 standard_sse_mode_p (enum machine_mode mode)
 {
@@ -6950,6 +6952,8 @@ standard_sse_mode_p (enum machine_mode m
     case V8SFmode:
     case V4DImode:
     case V4DFmode:
+      return 2;
+
     case V16QImode:
     case V8HImode:
     case V4SImode:
@@ -6963,8 +6967,10 @@ standard_sse_mode_p (enum machine_mode m
     }
 }
 
-/* Return 1 if X is FP constant we can load to SSE register w/o using memory.
- */
+/* Return 1 if X is all 0s.  For all 1s, return 2 if X is in 128bit
+   SSE modes and SSE2 is enabled,  return 3 if X is in 256bit AVX
+   modes and AVX is enabled.  */
+
 int
 standard_sse_constant_p (rtx x)
 {
@@ -6972,9 +6978,16 @@ standard_sse_constant_p (rtx x)
 
   if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x)))
     return 1;
-  if (vector_all_ones_operand (x, mode)
-      && standard_sse_mode_p (mode))
-    return TARGET_SSE2 ? 2 : -1;
+  if (vector_all_ones_operand (x, mode))
+    switch (standard_sse_mode_p (mode))
+      {
+      case 1:
+	return TARGET_SSE2 ? 2 : -2;
+      case 2:
+	return TARGET_AVX ? 3 : -3;
+      default:
+	break;
+      }
 
   return 0;
 }
@@ -7014,12 +7027,6 @@ standard_sse_constant_opcode (rtx insn, 
 	  case MODE_TI:
 	    return "vpcmpeqd\t%0, %0, %0";
 	    break;
-	  case MODE_V8SF:
-	  case MODE_V4DF:
-	  case MODE_OI:
-	    return "vpcmpeqd\t%0, %0, %0\n\t"
-		   "vperm2f128\t{$0x0, %0, %0, %0|%0, %0, %0, 0x0}";
-	    break;
 	  default:
 	    gcc_unreachable ();
 	}