[PATCH, i386]: Fix PR target/36992

[H.J. Lu]

On Sat, Aug 2, 2008 at 11:54 AM, Richard Guenther
<richard.guenther@gmail.com> wrote:
> On Sat, Aug 2, 2008 at 8:41 PM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> Hello!
>>
>> Attached patch fixes PR target/36992 by adding a SSE reg-reg alternative to
>> vec_concatv2di insn patterns, following updated documentation from Intel.
>> "movq xmm, xmm" insn fills upper 64bit with zeroes also for reg-reg moves.
>
> "updated documentation"?  Are we sure all implementations follow this
> updated documentation?  I guess a runtime testcase checking this would be
> useful ;)
>

From AMD64 spec for movq:

Moves a 64-bit value in one of the following ways:
• from the low-order 64 bits of an XMM register or a 64-bit memory
location to the low-order 64 bits
of another XMM register, with zero-extension to 128 bits
• from the low-order 64 bits of an XMM register to the low-order 64
bits of another XMM register,
with zero-extension to 128 bits or to a 64-bit memory location




-- 
H.J.