[PATCH, i386]: Fix PR target/36992

[Uros Bizjak]

Hello!

Attached patch fixes PR target/36992 by adding a SSE reg-reg alternative 
to vec_concatv2di insn patterns, following updated documentation from 
Intel. "movq xmm, xmm" insn fills upper 64bit with zeroes also for 
reg-reg moves.

The testcase from PR also exposes wrong register allocation choice for 
-O0. DImode value is passed through MMX register for 64bit targets, and 
we want to avoid this due to mmx-x87 register file switching problems. 
This problem is fixed by penalizing SSE register allocation to avoid 
SSE->MMX conversions.

The patch was bootstrapped and regression tested on x86_64 {,-m32}.

2008-08-02  Uros Bizjak  <ubizjak@gmail.com>

    PR target/36992
    * config/i386/sse.md (vec_concatv2di): Add Y2 constraint to
    alternative 0 of operand 1.
    (*vec_concatv2di_rex64_sse): Ditto.
    (*vec_concatv2di_rex64_sse4_1): Add x constraint to alternative 0
    of operand 1.
    (*sse2_storeq_rex64): Penalize allocation of "r" registers.
    * config/i386/mmx.md (*mov<mode>_internal_rex64): Penalize allocation
    of "Y2" registers to avoid SSE <-> MMX conversions for DImode moves.
    (*movv2sf_internal_rex64): Ditto.

testsuite/ChangeLog:

2008-08-02  Uros Bizjak  <ubizjak@gmail.com>

    PR target/36992
    * gcc.target/i386/pr36992-1.c: New test.
    * gcc.target/i386/pr36992-2.c: Ditto.

Uros.
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