[RFA] The Integrated Register Allocator
Vladimir Makarov
vmakarov@redhat.com
Sun Apr 6 09:07:00 GMT 2008
Bernd Schmidt wrote:
> I've briefly played with the IRA patch. Below is a patch necessary to
> make it work with the Blackfin port.
>
> I've not made any measurements yet, but visually inspecting the
> results reveals at least one code generation regression which shows up
> fairly often. In case you want to investigate, I'm providing some
> details.
>
> To reproduce, compile the attached testcase (a3.i) with a bfin-elf
> compiler:
> ./cc1 a3.i -O2 -fomit-frame-pointer -o a3.1.s
> ./cc1 a3.i -O2 -fira -fomit-frame-pointer -o a3.2.s
>
> The difference is as follows:
>
> P2.H = _reg_known_value_size; | P2 = [P5+4];
> P2.L = _reg_known_value_size; | P1.H = _reg_known_value_size;
> P1 = [P5+4]; | P1.L = _reg_known_value_size;
> P2 = [P2]; | R0 = [P1];
> cc =P1<P2 (iu); | R1 = P2;
> > cc =R1<R0 (iu);
>
> One extra register move is generated in reload, because IRA produces
> an insn whose register class requirements aren't met.
>
I think the problem has been fixed. Now I have on ira branch
_clear_reg_alias_info:
[--sp] = ( p5:5 );
P5 = R0;
R1 = 71 (X);
[--SP] = RETS;
SP += -20;
R0 = W [P5] (Z);
cc =R0==R1;
if cc jump .L2;
R0 = 1055 (X);
[SP+12] = R0;
R0.H = ___FUNCTION__.1366;
R0.L = ___FUNCTION__.1366;
R2.H = .LC0;
[SP+16] = R0;
R2.L = .LC0;
R0 = P5;
call _rtl_check_failed_code1;
.L2:
P1.H = _reg_known_value_size;
P1.L = _reg_known_value_size;
P2 = [P5+4];
P1 = [P1];
cc =P2<P1 (iu);
if !cc jump .L4;
P0 = 34 (X);
cc =P2<=P0 (iu);
if cc jump .L4;
P1.H = _reg_known_value;
P1.L = _reg_known_value;
P1 = [P1];
P2 = P1 + (P2 << 2);
[P2] = P5;
.L4:
SP += 20;
RETS = [SP++];
( p5:5 ) = [sp++];
rts;
The patch responsible for this is
http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00400.html
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