PATCH: Enable Intel AES/CLMUL

[Jakub Jelinek]

On Fri, Apr 04, 2008 at 04:33:51PM +0200, Uros Bizjak wrote:
> This will work just fine even without SSE (although a warning about
> changed ABI will be issued). We can even add AES functionality to the
> library this way (hint, hint ;)
> 
> And using intrinsic, the situation will be actually just reversed to
> the situation you described below.

This doesn't make sense.  The aes instructions use SSE2 registers,
so IMNSHO you really have to enable sse2 to be able to emit aes/pclmul
instructions.  So it makes perfect sense for -maes to enable -msse2.

(define_insn "aesenc"
  [(set (match_operand:V2DI 0 "register_operand" "=x")
       (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
                      (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
                     UNSPEC_AESENC))]
  "TARGET_AES"
  "aesenc\t{%2, %0|%0, %2}"
  [(set_attr "type" "sselog1")
   (set_attr "prefix_extra" "1")
   (set_attr "mode" "TI")])

With -mno-sse "x" constraint is actually NO_REGS, how could that ever match?
And V2DI mode for SSE regs is SSE2+ only.

	Jakub