PR target/33396

[Jan Hubicka]

Hi,
I forgot TARGET_SSE_MATH in the conditional for SSE floatsisf* patterns
causing bootstrap failure with 32bit generic when
TARGET_USE_VECTOR_CONVERTS is used.

Bootstrapped/regtested i686-linux with that change and comitted.
Honza

2007-09-12  Jan Hubicka  <jh@suse.cz>

	PR target/33393
	* i386.md (floatsisf2_mixed_memory, floatsisf2_sse_memory): Disable for
	!SSE_MATH
Index: config/i386/i386.md
===================================================================
*** config/i386/i386.md	(revision 128412)
--- config/i386/i386.md	(working copy)
***************
*** 3927,3933 ****
    [(set (match_operand:DF 0 "register_operand" "")
          (float_extend:DF
  	  (match_operand:SF 1 "nonimmediate_operand" "")))]
!   "TARGET_USE_VECTOR_CONVERTS && !optimize_size 
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (float_extend:V2DF
--- 3927,3933 ----
    [(set (match_operand:DF 0 "register_operand" "")
          (float_extend:DF
  	  (match_operand:SF 1 "nonimmediate_operand" "")))]
!   "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size 
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (float_extend:V2DF
***************
*** 4063,4069 ****
    [(set (match_operand:SF 0 "register_operand" "")
          (float_truncate:SF
  	  (match_operand:DF 1 "nonimmediate_operand" "")))]
!   "TARGET_USE_VECTOR_CONVERTS && !optimize_size 
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (vec_concat:V4SF
--- 4063,4069 ----
    [(set (match_operand:SF 0 "register_operand" "")
          (float_truncate:SF
  	  (match_operand:DF 1 "nonimmediate_operand" "")))]
!   "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size 
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (vec_concat:V4SF
***************
*** 4876,4882 ****
  (define_insn "*floatsisf2_sse_vector_nointernunit"
    [(set (match_operand:SF 0 "register_operand" "=x")
  	(float:SF (match_operand:SI 1 "memory_operand" "m")))]
!   "flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && !TARGET_INTER_UNIT_MOVES"
    "#"
    [(set_attr "type" "multi")])
--- 4876,4883 ----
  (define_insn "*floatsisf2_sse_vector_nointernunit"
    [(set (match_operand:SF 0 "register_operand" "=x")
  	(float:SF (match_operand:SI 1 "memory_operand" "m")))]
!   "TARGET_SSE_MATH && flag_trapping_math
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && !TARGET_INTER_UNIT_MOVES"
    "#"
    [(set_attr "type" "multi")])
***************
*** 4884,4890 ****
  (define_insn "*floatsisf2_sse_vector_internunit"
    [(set (match_operand:SF 0 "register_operand" "=x,x")
  	(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,x")))]
!   "flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && TARGET_INTER_UNIT_MOVES"
    "#"
    [(set_attr "type" "multi")])
--- 4885,4892 ----
  (define_insn "*floatsisf2_sse_vector_internunit"
    [(set (match_operand:SF 0 "register_operand" "=x,x")
  	(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,x")))]
!   "TARGET_SSE_MATH && flag_trapping_math
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && TARGET_INTER_UNIT_MOVES"
    "#"
    [(set_attr "type" "multi")])
***************
*** 4921,4927 ****
  (define_insn "*floatsisf2_sse_vector"
    [(set (match_operand:SF 0 "register_operand" "=x")
  	(float:SF (match_operand:SI 1 "register_operand" "x")))]
!   "!flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && !TARGET_INTER_UNIT_MOVES"
    "cvtdq2ps\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseicvt")
--- 4923,4930 ----
  (define_insn "*floatsisf2_sse_vector"
    [(set (match_operand:SF 0 "register_operand" "=x")
  	(float:SF (match_operand:SI 1 "register_operand" "x")))]
!   "TARGET_SSE_MATH && !flag_trapping_math
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && !TARGET_INTER_UNIT_MOVES"
    "cvtdq2ps\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseicvt")