SSE conversion optimization

H.J. Lu hjl@lucon.org
Mon Sep 10 00:59:00 GMT 2007


On Sun, Sep 09, 2007 at 07:49:04PM +0200, Jan Hubicka wrote:
> Hi,
> this is variant of patch I comitted.  It change only amdfam10 codegen so
> far until we figure out what would be best setting for generic and
> core2.
> For AMDFAM10 it is also better to offload to memory operand of
> DImode->SF/DFmode conversions I will try to do next. 
> 

There are 2 typos. It should be cvtdq2ps, not cvtpq2ps.


H.J.
---
2007-09-09  H.J. Lu  <hongjiu.lu@intel.com>

	* i386.md (*floatsisf2_mixed_vector): Use cvtdq2ps instead
	of cvtpq2ps.
	(*floatsisf2_sse_vector): Likewise.

--- gcc/config/i386/i386.md.typo	2007-09-09 13:29:47.000000000 -0700
+++ gcc/config/i386/i386.md	2007-09-09 16:52:46.000000000 -0700
@@ -4850,7 +4850,7 @@
   "TARGET_MIX_SSE_I387 && !flag_trapping_math 
    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
   "@
-   cvtpq2ps\t{%1, %0|%0, %1}
+   cvtdq2ps\t{%1, %0|%0, %1}
    fild%z1\t%1
    #"
   [(set_attr "type" "sseicvt,fmov,multi")
@@ -4927,7 +4927,7 @@
 	(float:SF (match_operand:SI 1 "register_operand" "x")))]
   "!flag_trapping_math && TARGET_USE_VECTOR_CONVERTS && !optimize_size
    && !TARGET_INTER_UNIT_MOVES"
-  "cvtpq2ps\t{%1, %0|%0, %1}"
+  "cvtdq2ps\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "double")



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