[patch] Fixed-point patch 8/10

Fu, Chao-Ying fu@mips.com
Thu Sep 6 00:06:00 GMT 2007


Richard Sandiford wrote:
> Subject: Re: [patch] Fixed-point patch 8/10
> 
> 
> >   Thanks a lot!  The new diff file is attached.
> 
> Thanks for the updates, this looks great.  OK to install when
> the time comes.
> 
> Richard
> 

Hi, Richard,

  To improve the performance of non-saturating operations, we
add several add/sub/mul patterns in mips-fixed.md.  We try to
use saturating instructions for non-saturating operations.

Ex 1:
+;; For non-saturating unsigned vector add, we can use saturating instructions
+;; because the overflowed/underflowed result is undefined.
+(define_insn "add<mode>3"
+  [(parallel
+    [(set (match_operand:VUADDSUB 0 "register_operand" "=d")
+         (plus:VUADDSUB (match_operand:VUADDSUB 1 "register_operand" "d")
+                        (match_operand:VUADDSUB 2 "register_operand" "d")))
+     (set (reg:CCDSP CCDSP_OU_REGNUM)
+         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
+  ""
+  "addu_s.<uaddsubfmt>\t%0,%1,%2"
+  [(set_attr "type" "arith")
+   (set_attr "mode" "<IMODE>")])
+
+;; For non-saturating signed vector add, we can use saturating instructions
+;; because the overflowed/underflowed result is undefined.
+(define_insn "add<mode>3"
+  [(parallel
+    [(set (match_operand:VADDSUB 0 "register_operand" "=d")
+         (plus:VADDSUB (match_operand:VADDSUB 1 "register_operand" "d")
+                       (match_operand:VADDSUB 2 "register_operand" "d")))
+     (set (reg:CCDSP CCDSP_OU_REGNUM)
+         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
+  "TARGET_DSP"
+  "addq_s.<addsubfmt>\t%0,%1,%2"
+  [(set_attr "type" "arith")
+   (set_attr "mode" "<IMODE>")])

Ex 2:
+;; For non-saturating unsigned vector sub, we can use saturating instructions
+;; because the overflowed/underflowed result is undefined.
+(define_insn "sub<mode>3"
+  [(parallel
+    [(set (match_operand:VUADDSUB 0 "register_operand" "=d")
+         (minus:VUADDSUB (match_operand:VUADDSUB 1 "register_operand" "d")
+                         (match_operand:VUADDSUB 2 "register_operand" "d")))
+     (set (reg:CCDSP CCDSP_OU_REGNUM)
+         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
+  ""
+  "subu_s.<uaddsubfmt>\t%0,%1,%2"
+  [(set_attr "type" "arith")
+   (set_attr "mode" "<IMODE>")])
+
+;; For non-saturating signed vector sub, we can use saturating instructions
+;; because the overflowed/underflowed result is undefined.
+(define_insn "sub<mode>3"
+  [(parallel
+    [(set (match_operand:VADDSUB 0 "register_operand" "=d")
+         (minus:VADDSUB (match_operand:VADDSUB 1 "register_operand" "d")
+                        (match_operand:VADDSUB 2 "register_operand" "d")))
+     (set (reg:CCDSP CCDSP_OU_REGNUM)
+         (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
+  "TARGET_DSP"
+  "subq_s.<addsubfmt>\t%0,%1,%2"
+  [(set_attr "type" "arith")
+   (set_attr "mode" "<IMODE>")])

Ex 3:
+;; For non-saturating mul, we can use saturating instructions
+;; because the overflowed/underflowed result is undefined.
+(define_insn "mul<mode>3"
+  [(parallel
+    [(set (match_operand:MULQ 0 "register_operand" "=d")
+          (mult:MULQ (match_operand:MULQ 1 "register_operand" "d")
+                    (match_operand:MULQ 2 "register_operand" "d")))
+     (set (reg:CCDSP CCDSP_OU_REGNUM)
+          (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH))
+     (clobber (match_scratch:DI 3 "=x"))])]
+  ""
+  "mulq_rs.<mulqfmt>\t%0,%1,%2"
+  [(set_attr "type"     "imul3")
+   (set_attr "mode"     "<IMODE>")])

  We also added new tests to the patch #10 to check if GCC can generate
all instructions for fixed-point types.

  Is this updated patch ok?  Thanks a lot!

Regards,
Chao-ying
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