[PATCH,SH] Add SH2A new instructions 6/6

[Naveen H.S.]

Hi,

Thank you for all the valuable suggestions and modifying the patch. We
will 
take care of all the comments and suggestions in our future works as
well. 
These bit instructions were implemented prior to the patch which
modified 
the bit patterns. This patch was posted in the following link
http://gcc.gnu.org/ml/gcc-patches/2007-07/msg01531.html

The implemented bit instructions resulted in very good optimization of
the 
bit operations. However, the bit instructions are not getting generated
more 
frequently after the above mentioned patch. Please suggest the
modifications 
to be done on the present patch to generate bit instructions as earlier.

Please find attached the modified patch "sh2a6.patch" as per the
suggestions. 

ChangeLog
2007-10-25	Naveen.H.S naveen.hs@kpitcummins.com

	* config/sh/constraints.md: K03, K12, Sbw : New constraints.
	* config/sh/predicates.md (bitwise_memory_operand) : New
predicate.
	* config/sh/sh.c (print_operand): "f" bit operator
	"e" bitnot operator.
	"t" prints memory address of a register.
	* config/sh/sh.h (sh_args): Add condition for SH2A.
	* config/sh/sh.md (extendqisi2_compact): enable 4-byte mov.b 
	instructions.
	(extendqihi2): enable 4-byte mov.b instructions.
	(movqi_i): enable 4-byte mov.b instructions.
	(insv): Add conditions to generate BSET, BCLR and BST
instructions in 
	memory mode.
	(extv): Add conditions to generate BLD instruction in memory
mode.
	(extzv): Add conditions to generate BLD instruction in memory
mode.
	bclr_m2a, bset_m2a, bst_m2a, bld_m2a, bld_reg, *bld_regqi,
bld_reg1, 
	bld_regqi1, bldnot_m2a, band_m2a, bandnot_m2a, bor_m2a,
bornot_m2a, 
	bxor_m2a, bit_m2a, bitnot_m2a: New instructions.
	
Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune (INDIA) 
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