[AVR] Add new peephole .

Anatoly Sokolov aesok@post.ru
Sat Mar 31 11:57:00 GMT 2007


Hello.

  This patch adds new 'peephole2' in avr backend, which are merge two set:QI
insn for pair resisters in one set:HI. As result on 'avr4' and 'avr5' 
architectures instead of two MOV instructions one MOVW is generated.

2007-03-31  Anatoly Sokolov <aesok@post.ru>

	* config/avr/predicates.md (even_register_operand, 
	odd_register_operand): New predicates.
	* config/avr/avr.md (movw peephole2): New.
	(movw_r peephole2): New.


Index: gcc/config/avr/predicates.md
===================================================================
--- gcc/config/avr/predicates.md	(revision 123372)
+++ gcc/config/avr/predicates.md	(working copy)
@@ -28,6 +28,16 @@
   (and (match_code "reg")
        (match_test "REGNO (op) >= 16 && REGNO (op) <= 31")))
 
+(define_predicate "even_register_operand"
+  (and (match_code "reg")
+       (and (match_test "REGNO (op) <= 31")
+            (match_test "(REGNO (op) & 1) == 0"))))
+
+(define_predicate "odd_register_operand"
+  (and (match_code "reg")
+       (and (match_test "REGNO (op) <= 31")
+            (match_test "(REGNO (op) & 1) != 0"))))
+
 ;; SP register.
 (define_predicate "stack_register_operand"
   (and (match_code "reg")
Index: gcc/config/avr/avr.md
===================================================================
--- gcc/config/avr/avr.md	(revision 123372)
+++ gcc/config/avr/avr.md	(working copy)
@@ -283,6 +283,34 @@
   [(set_attr "length" "2,6,7,2,6,5,2")
    (set_attr "cc" "none,clobber,clobber,none,clobber,none,none")])
 
+(define_peephole2 ; movw
+  [(set (match_operand:QI 0 "even_register_operand" "")
+        (match_operand:QI 1 "even_register_operand" ""))
+   (set (match_operand:QI 2 "odd_register_operand" "")
+        (match_operand:QI 3 "odd_register_operand" ""))]
+  "(AVR_HAVE_MOVW
+    && REGNO (operands[0]) == REGNO (operands[2]) - 1
+    && REGNO (operands[1]) == REGNO (operands[3]) - 1)"
+  [(set (match_dup 4) (match_dup 5))]
+  {
+    operands[4] = gen_rtx_REG (HImode, REGNO (operands[0]));
+    operands[5] = gen_rtx_REG (HImode, REGNO (operands[1]));
+  })
+
+(define_peephole2 ; movw_r
+  [(set (match_operand:QI 0 "odd_register_operand" "")
+        (match_operand:QI 1 "odd_register_operand" ""))
+   (set (match_operand:QI 2 "even_register_operand" "")
+        (match_operand:QI 3 "even_register_operand" ""))]
+  "(AVR_HAVE_MOVW
+    && REGNO (operands[2]) == REGNO (operands[0]) - 1
+    && REGNO (operands[3]) == REGNO (operands[1]) - 1)"
+  [(set (match_dup 4) (match_dup 5))]
+  {
+    operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));
+    operands[5] = gen_rtx_REG (HImode, REGNO (operands[3]));
+  })
+
 ;;==========================================================================
 ;; move double word (32 bit)
 

Anatoly.



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