Split MIPS xfer type attributes into mfc and mtc

Joseph S. Myers joseph@codesourcery.com
Fri Mar 23 16:17:00 GMT 2007


This patch splits the MIPS "xfer" instruction type into "mfc" and
"mtc".  The use for this is illustrated in the sb1 and sr71k changes,
and it will be further used in other scheduling descriptions to be
submitted.

Tested with cross to mips-none-linux-gnu.  OK to commit?

2007-03-23  Joseph Myers  <joseph@codesourcery.com>

	* config/mips/mips.md (type, hazard, *movdi_32bit,
	*movdi_gp32_fp64, *movdi_64bit, *movsi_internal, movcc,
	*movhi_internal, *movqi_internal, *movsf_hardfloat,
	*movdf_hardfloat_64bit, *movdf_hardfloat_32bit, *movdf_softfloat,
	movv2sf_hardfloat_64bit, load_df_low, load_df_high, store_df_high,
	mthc1, mfhc1): Change xfer instruction type to mfc and mtc, as
	applicable.
	(movcc): Change first xfer to multi.
	* config/mips/24k.md, config/mips/4100.md, config/mips/4300.md,
	config/mips/5000.md, config/mips/5400.md, config/mips/5500.md,
	config/mips/5k.md, config/mips/7000.md, config/mips/9000.md,
	config/mips/generic.md: Change reservations using "xfer" to use
	"mfc,mtc".
	* config/mips/sb1.md (ir_sb1_mtxfer): Use "mtc" instead of
	examining mode.
	(ir_sb1_mfxfer): Use "mfc" instead of examining mode.
	* config/mips/sr71k.md (ir_sr70_xfer_from): Use "mfc" instead of
	examining mode.
	(ir_sr70_xfer_to): Use "mtc" instead of examining mode.

Index: config/mips/4100.md
===================================================================
--- config/mips/4100.md	(revision 123157)
+++ config/mips/4100.md	(working copy)
@@ -24,7 +24,7 @@
 
 (define_insn_reservation "r4100_load" 2
   (and (eq_attr "cpu" "r4100,r4120")
-       (eq_attr "type" "load,fpload,fpidxload,xfer"))
+       (eq_attr "type" "load,fpload,fpidxload,mfc,mtc"))
   "alu")
 
 (define_insn_reservation "r4100_imul_si" 1
Index: config/mips/5000.md
===================================================================
--- config/mips/5000.md	(revision 123157)
+++ config/mips/5000.md	(working copy)
@@ -24,7 +24,7 @@
 
 (define_insn_reservation "r5k_load" 2
   (and (eq_attr "cpu" "r5000")
-       (eq_attr "type" "load,fpload,fpidxload,xfer"))
+       (eq_attr "type" "load,fpload,fpidxload,mfc,mtc"))
   "alu")
 
 (define_insn_reservation "r5k_imul_si" 5
Index: config/mips/7000.md
===================================================================
--- config/mips/7000.md	(revision 123157)
+++ config/mips/7000.md	(working copy)
@@ -146,7 +146,7 @@
 ;; Move to/from fp coprocessor.
 (define_insn_reservation "rm7_ixfer" 2
   (and (eq_attr "cpu" "r7000")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "rm7_iaddsub")
 
 (define_insn_reservation "rm7_ibr" 3
Index: config/mips/9000.md
===================================================================
--- config/mips/9000.md	(revision 123157)
+++ config/mips/9000.md	(working copy)
@@ -98,7 +98,7 @@
 
 (define_insn_reservation "rm9k_xfer" 2
   (and (eq_attr "cpu" "r9000")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "rm9k_m")
 
 (define_insn_reservation "rm9k_fquick" 2
Index: config/mips/5400.md
===================================================================
--- config/mips/5400.md	(revision 123157)
+++ config/mips/5400.md	(working copy)
@@ -50,7 +50,7 @@
 ;; Move to/from FPU registers
 (define_insn_reservation "ir_vr54_xfer" 2
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_hilo" 1
Index: config/mips/generic.md
===================================================================
--- config/mips/generic.md	(revision 123157)
+++ config/mips/generic.md	(working copy)
@@ -36,7 +36,7 @@
   "alu")
 
 (define_insn_reservation "generic_xfer" 2
-  (eq_attr "type" "xfer")
+  (eq_attr "type" "mfc,mtc")
   "alu")
 
 (define_insn_reservation "generic_branch" 1
Index: config/mips/4300.md
===================================================================
--- config/mips/4300.md	(revision 123157)
+++ config/mips/4300.md	(working copy)
@@ -24,7 +24,7 @@
 
 (define_insn_reservation "r4300_load" 2
   (and (eq_attr "cpu" "r4300")
-       (eq_attr "type" "load,fpload,fpidxload,xfer"))
+       (eq_attr "type" "load,fpload,fpidxload,mfc,mtc"))
   "alu")
 
 (define_insn_reservation "r4300_imul_si" 5
Index: config/mips/5500.md
===================================================================
--- config/mips/5500.md	(revision 123157)
+++ config/mips/5500.md	(working copy)
@@ -51,7 +51,7 @@
 ;; Move to/from FPU registers
 (define_insn_reservation "ir_vr55_xfer" 2
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "vr55_dp0|vr55_dp1")
 
 (define_insn_reservation "ir_vr55_arith" 1
Index: config/mips/24k.md
===================================================================
--- config/mips/24k.md	(revision 123157)
+++ config/mips/24k.md	(working copy)
@@ -319,7 +319,7 @@
 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
 (define_insn_reservation "r24k_fxfer" 4
   (and (eq_attr "cpu" "24kf")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "r24k_fpu_iss")
 
 ;; --------------------------------------------------------------
@@ -435,7 +435,7 @@
 ;; fxfer (mfc1, mfhc1, mtc1, mthc1)
 (define_insn_reservation "r24kx_fxfer" 2
   (and (eq_attr "cpu" "24kx")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "r24kx_fpu_iss")
 
 ;; --------------------------------------------------------------
Index: config/mips/mips.md
===================================================================
--- config/mips/mips.md	(revision 123157)
+++ config/mips/mips.md	(working copy)
@@ -245,7 +245,8 @@
 ;; prefetch	memory prefetch (register + offset)
 ;; prefetchx	memory indexed prefetch (register + register)
 ;; condmove	conditional moves
-;; xfer		transfer to/from coprocessor
+;; mfc		transfer from coprocessor
+;; mtc		transfer to coprocessor
 ;; mthilo	transfer to hi/lo registers
 ;; mfhilo	transfer from hi/lo registers
 ;; const	load constant
@@ -277,7 +278,7 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 (define_attr "type"
-  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
+  "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
   (cond [(eq_attr "jal" "!unset") (const_string "call")
 	 (eq_attr "got" "load") (const_string "load")]
 	(const_string "unknown")))
@@ -406,7 +407,7 @@
 	      (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
 	 (const_string "delay")
 
-	 (and (eq_attr "type" "xfer")
+	 (and (eq_attr "type" "mfc,mtc")
 	      (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
 	 (const_string "delay")
 
@@ -3312,7 +3313,7 @@
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,arith,load,store,mthilo,mfhilo,mtc,load,mfc,store")
    (set_attr "mode"	"DI")
    (set_attr "length"   "8,16,*,*,8,8,8,*,8,*")])
 
@@ -3323,7 +3324,7 @@
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,arith,load,store,mthilo,mfhilo,fmove,xfer,fpload,xfer,fpstore")
+  [(set_attr "type"	"arith,arith,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
    (set_attr "mode"	"DI")
    (set_attr "length"   "8,16,*,*,8,8,4,8,*,8,*")])
 
@@ -3345,7 +3346,7 @@
    && (register_operand (operands[0], DImode)
        || reg_or_0_operand (operands[1], DImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
    (set_attr "mode"	"DI")
    (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
 
@@ -3441,7 +3442,7 @@
    && (register_operand (operands[0], SImode)
        || reg_or_0_operand (operands[1], SImode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,mfhilo,xfer,load,xfer,store")
+  [(set_attr "type"	"arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
    (set_attr "mode"	"SI")
    (set_attr "length"	"4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
 
@@ -3542,7 +3543,7 @@
 	(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
+  [(set_attr "type"	"multi,arith,load,store,mfc,mtc,fmove,fpload,fpstore")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8,4,*,*,4,4,4,*,*")])
 
@@ -3642,7 +3643,7 @@
     mtc1\t%1,%0
     mov.s\t%0,%1
     mt%0\t%1"
-  [(set_attr "type"	"arith,arith,load,store,xfer,xfer,fmove,mthilo")
+  [(set_attr "type"	"arith,arith,load,store,mfc,mtc,fmove,mthilo")
    (set_attr "mode"	"HI")
    (set_attr "length"	"4,4,*,*,4,4,4,4")])
 
@@ -3749,7 +3750,7 @@
     mtc1\t%1,%0
     mov.s\t%0,%1
     mt%0\t%1"
-  [(set_attr "type"	"arith,arith,load,store,xfer,xfer,fmove,mthilo")
+  [(set_attr "type"	"arith,arith,load,store,mfc,mtc,fmove,mthilo")
    (set_attr "mode"	"QI")
    (set_attr "length"	"4,4,*,*,4,4,4,4")])
 
@@ -3819,7 +3820,7 @@
    && (register_operand (operands[0], SFmode)
        || reg_or_0_operand (operands[1], SFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+  [(set_attr "type"	"fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4,4,*,*,*,4,4,4,*,*")])
 
@@ -3864,7 +3865,7 @@
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+  [(set_attr "type"	"fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4,4,*,*,*,4,4,4,*,*")])
 
@@ -3876,7 +3877,7 @@
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+  [(set_attr "type"	"fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4,8,*,*,*,8,8,8,*,*")])
 
@@ -3887,7 +3888,7 @@
    && (register_operand (operands[0], DFmode)
        || reg_or_0_operand (operands[1], DFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type"	"arith,load,store,xfer,xfer,fmove")
+  [(set_attr "type"	"arith,load,store,mfc,mtc,fmove")
    (set_attr "mode"	"DF")
    (set_attr "length"	"8,*,*,4,4,4")])
 
@@ -3958,7 +3959,7 @@
    && (register_operand (operands[0], V2SFmode)
        || reg_or_0_operand (operands[1], V2SFmode))"
   { return mips_output_move (operands[0], operands[1]); }
-  [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
+  [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
    (set_attr "mode" "SF")
    (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
 
@@ -4018,7 +4019,7 @@
   operands[0] = mips_subword (operands[0], 0);
   return mips_output_move (operands[0], operands[1]);
 }
-  [(set_attr "type"	"xfer,fpload")
+  [(set_attr "type"	"mtc,fpload")
    (set_attr "mode"	"SF")])
 
 ;; Load the high word of operand 0 from operand 1, preserving the value
@@ -4033,7 +4034,7 @@
   operands[0] = mips_subword (operands[0], 1);
   return mips_output_move (operands[0], operands[1]);
 }
-  [(set_attr "type"	"xfer,fpload")
+  [(set_attr "type"	"mtc,fpload")
    (set_attr "mode"	"SF")])
 
 ;; Store the high word of operand 1 in operand 0.  The corresponding
@@ -4047,7 +4048,7 @@
   operands[1] = mips_subword (operands[1], 1);
   return mips_output_move (operands[0], operands[1]);
 }
-  [(set_attr "type"	"xfer,fpstore")
+  [(set_attr "type"	"mfc,fpstore")
    (set_attr "mode"	"SF")])
 
 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
@@ -4059,7 +4060,7 @@
 		    UNSPEC_MTHC1))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
   "mthc1\t%z1,%0"
-  [(set_attr "type"	"xfer")
+  [(set_attr "type"	"mtc")
    (set_attr "mode"	"SF")])
 
 ;; Move high word of operand 1 to operand 0 using mfhc1.  The corresponding
@@ -4070,7 +4071,7 @@
 		    UNSPEC_MFHC1))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
   "mfhc1\t%0,%1"
-  [(set_attr "type"	"xfer")
+  [(set_attr "type"	"mfc")
    (set_attr "mode"	"SF")])
 
 ;; Insn to initialize $gp for n32/n64 abicalls.  Operand 0 is the offset
Index: config/mips/5k.md
===================================================================
--- config/mips/5k.md	(revision 123157)
+++ config/mips/5k.md	(working copy)
@@ -226,5 +226,5 @@
 ;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
 (define_insn_reservation "r5kf_fxfer" 2
   (and (eq_attr "cpu" "5kf")
-       (eq_attr "type" "xfer"))
+       (eq_attr "type" "mfc,mtc"))
   "r5k_ixu_arith+r5kf_fpu_arith")
Index: config/mips/sb1.md
===================================================================
--- config/mips/sb1.md	(revision 123157)
+++ config/mips/sb1.md	(working copy)
@@ -415,16 +415,14 @@
 
 (define_insn_reservation "ir_sb1_mtxfer" 5
   (and (eq_attr "cpu" "sb1,sb1a")
-       (and (eq_attr "type" "xfer")
-	    (match_operand 0 "fpr_operand")))
+       (eq_attr "type" "mtc"))
   "sb1_fp0")
 
 ;; mfc1 latency 1 cycle.  
 
 (define_insn_reservation "ir_sb1_mfxfer" 1
   (and (eq_attr "cpu" "sb1,sb1a")
-       (and (eq_attr "type" "xfer")
-	    (not (match_operand 0 "fpr_operand"))))
+       (eq_attr "type" "mfc"))
   "sb1_fp0")
 
 ;; ??? Can deliver at most 1 result per every 6 cycles because of issue
Index: config/mips/sr71k.md
===================================================================
--- config/mips/sr71k.md	(revision 123157)
+++ config/mips/sr71k.md	(working copy)
@@ -173,14 +173,12 @@
 ;; resources simultaneously
 (define_insn_reservation "ir_sr70_xfer_from" 6
   (and (eq_attr "cpu" "sr71000")
-       (and (eq_attr "type" "xfer")
-	    (eq_attr "mode" "!SF,DF,FPSW")))
+       (eq_attr "type" "mfc"))
   "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
 
 (define_insn_reservation "ir_sr70_xfer_to" 9
   (and (eq_attr "cpu" "sr71000")
-       (and (eq_attr "type" "xfer")
-	    (eq_attr "mode" "SF,DF")))
+       (eq_attr "type" "mtc"))
   "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
 
 (define_insn_reservation "ir_sr70_hilo" 1

-- 
Joseph S. Myers
joseph@codesourcery.com



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