[patch] m68k: ISAC corrections (Part 1)

[Kazu Hirata]

Hi,

Attached is a patch to correct the ISAC support.

Zero-extend and sign-extend moves are available on both TARGET_ISAB
and TARGET_ISAC.  The ff1 instruction (or clz in the gcc terms) is
available on both TARGET_ISAAPLUS and TARGET_ISAC.  This patch
introduces ISA_HAS_MVS_MVZ and ISA_HAS_FF1 to indicate the
availability of these instructions.

Tested by building m68k-elf.  OK to apply?

Kazu Hirata

2007-06-14  Nathan Sidwell  <nathan@codesourcery.com>

	* config/m68k/m68k.h (ISA_HAS_FF1, ISA_HAS_MVS_MVZ): New.
	* config/m68k/m68k.md: Use ISA_HAS_FF1 and ISA_HAS_MVS_MVZ as
	appropriate.

Index: gcc/config/m68k/m68k.h
===================================================================
--- gcc/config/m68k/m68k.h	(revision 125739)
+++ gcc/config/m68k/m68k.h	(working copy)
@@ -245,6 +245,10 @@ Boston, MA 02110-1301, USA.  */
 #define TARGET_ISAB		((m68k_cpu_flags & FL_ISA_B) != 0)
 #define TARGET_ISAC		((m68k_cpu_flags & FL_ISA_C) != 0)
 
+/* Some instructions are common to more than one ISA.  */
+#define ISA_HAS_MVS_MVZ	(TARGET_ISAB || TARGET_ISAC)
+#define ISA_HAS_FF1	(TARGET_ISAAPLUS || TARGET_ISAC)
+
 #define TUNE_68000	(m68k_tune == u68000)
 #define TUNE_68010	(m68k_tune == u68010)
 #define TUNE_68000_10	(TUNE_68000 || TUNE_68010)
Index: gcc/config/m68k/m68k.md
===================================================================
--- gcc/config/m68k/m68k.md	(revision 125739)
+++ gcc/config/m68k/m68k.md	(working copy)
@@ -1391,7 +1391,7 @@ (define_insn_and_split "*zero_extendsidi
 (define_insn "*zero_extendhisi2_cf"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
-  "TARGET_ISAB"
+  "ISA_HAS_MVS_MVZ"
   "mvz%.w %1,%0")
 
 (define_insn "zero_extendhisi2"
@@ -1415,7 +1415,7 @@ (define_insn "*zero_extendqihi2"
 (define_insn "*zero_extendqisi2_cfv4"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
-  "TARGET_ISAB"
+  "ISA_HAS_MVS_MVZ"
   "mvz%.b %1,%0")
 
 (define_insn "zero_extendqisi2"
@@ -1429,7 +1429,7 @@ (define_insn "zero_extendqisi2"
 (define_split
   [(set (match_operand 0 "register_operand" "")
 	(zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
-  "!TARGET_ISAB
+  "!ISA_HAS_MVS_MVZ
    && reload_completed
    && reg_mentioned_p (operands[0], operands[1])"
   [(set (strict_low_part (match_dup 2))
@@ -1445,7 +1445,7 @@ (define_split
 (define_split
   [(set (match_operand 0 "register_operand" "")
 	(zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
-  "!TARGET_ISAB && reload_completed"
+  "!ISA_HAS_MVS_MVZ && reload_completed"
   [(set (match_dup 0)
 	(const_int 0))
    (set (strict_low_part (match_dup 2))
@@ -1463,7 +1463,7 @@ (define_insn "extendqidi2"
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_ISAB)
+  if (ISA_HAS_MVS_MVZ)
     return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
   if (TARGET_68020 || TARGET_COLDFIRE)
     {
@@ -1489,7 +1489,7 @@ (define_insn "extendhidi2"
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_ISAB)
+  if (ISA_HAS_MVS_MVZ)
     return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
   if (TARGET_68020 || TARGET_COLDFIRE)
     return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
@@ -1567,14 +1567,14 @@ (define_insn "*cfv4_extendhisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(sign_extend:SI
 	 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
-  "TARGET_ISAB"
+  "ISA_HAS_MVS_MVZ"
   "mvs%.w %1,%0")
 
 (define_insn "*68k_extendhisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
 	(sign_extend:SI
 	 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
-  "!TARGET_ISAB"
+  "!ISA_HAS_MVS_MVZ"
 {
   if (ADDRESS_REG_P (operands[0]))
     return "move%.w %1,%0";
@@ -1596,13 +1596,13 @@ (define_expand "extendqisi2"
 (define_insn "*cfv4_extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
-  "TARGET_ISAB"
+  "ISA_HAS_MVS_MVZ"
   "mvs%.b %1,%0")
 
 (define_insn "*68k_extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  "TARGET_68020 || (TARGET_COLDFIRE && !TARGET_ISAB)"
+  "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
   "extb%.l %0")
 
 ;; Conversions between float and double.
@@ -3114,7 +3114,7 @@ (define_insn "udivmodhi4"
 	(umod:HI (match_dup 1) (match_dup 2)))]
   "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
 {
-  if (TARGET_ISAB)
+  if (ISA_HAS_MVS_MVZ)
     output_asm_insn (MOTOROLA ?
       "mvz%.w %0,%0\;divu%.w %2,%0" :
       "mvz%.w %0,%0\;divu %2,%0",
@@ -3238,7 +3238,7 @@ (define_insn "andsi3_5200"
 		(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
   "TARGET_COLDFIRE"
 {
-  if (TARGET_ISAB
+  if (ISA_HAS_MVS_MVZ
       && DATA_REG_P (operands[0])
       && GET_CODE (operands[2]) == CONST_INT)
     {
@@ -4005,7 +4005,7 @@ (define_insn "abs<mode>2_cf"
 (define_insn "clzsi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
  	(clz:SI (match_operand:SI 1 "register_operand" "0")))]
-  "TARGET_ISAAPLUS || TARGET_ISAC"
+  "ISA_HAS_FF1"
   "ff1 %0")
 
 ;; one complement instructions