PATCH (SPU): Add enhanced Double Precision (eDP) support on SPU

[Sa Liu]

"Andrew Pinski" <pinskia@gmail.com> wrote on 12.06.2007 02:06:52:

> I have a couple of comments about this patch.
> Why are you changing the formating of some switch statements:
> @@ -679,77 +712,28 @@ spu_emit_branch_or_set (int is_set, enum
>        if (trunc_int_for_mode (val, GET_MODE (spu_compare_op0)) == val)
>         switch (code)
>           {
> -         case GE:
> -           spu_compare_op1 = GEN_INT (val);
> -           code = GT;
> -           break;
> -         case LT:
> -           spu_compare_op1 = GEN_INT (val);
> -           code = LE;
> -           break;
> -         case GEU:
> -           spu_compare_op1 = GEN_INT (val);
> -           code = GTU;
> -           break;
> -         case LTU:
> -           spu_compare_op1 = GEN_INT (val);
> -           code = LEU;
> -           break;
> -         default:
> -           break;
> +         case GE:  spu_compare_op1 = GEN_INT (val); code = GT; break;
> +         case LT:  spu_compare_op1 = GEN_INT (val); code = LE; break;
> +         case GEU: spu_compare_op1 = GEN_INT (val); code = GTU; break;
> +         case LTU: spu_compare_op1 = GEN_INT (val); code = LEU; break;
> +         default: break;
>           }
>      }
> 
> etc.

Just to have a clear view of all the comparison operands. If this is not 
GCC code convention I can change them back.

> 
> You might want to add GTY(()) to the following external declarations:
> +extern int spu_arch;
> +extern int spu_tune;
> 
> So that PCH can be correct.

Ok.

> 
> Also is there a way to detect at runtime if a spu supports the
> enhanced double precusion instructions?  Which is needed so that
> fast-math-vect-reduc-7.c runs on non edp machines.

fast-math-vect-reduc-7.c will work on non-edp machines, because there are 
spu intrinsics using cell instructions to emulate edp instructions (only 
for vector type), in order to achieve the same result as on edp machines.
 
Thanks,
Sa