MIPS 74k scheduler adjustments

[Richard Sandiford]

"Fu, Chao-Ying" <fu@mips.com> writes:
> Joseph S. Myers wrote:
>> This patch adjusts the MIPS 74k scheduler to reflect that certain 
>> arithmetic instructions take only 1 cycle.  This in turn 
>> requires various 
>> instructions to be marked as "logical", "signext" or "move" 
>> instead of 
>> "arith".
>> 
>> Tested with no regressions with cross to mips-linux-gnu.  OK 
>> to commit?
>> 
>> 2007-07-04  David Ung  <davidu@mips.com>
>>             Joseph Myers  <joseph@codesourcery.com>
>> 
>> 	gcc/
>> 	* config/mips/mips.md (type): Add logical, signext and move.
>> 	(one_cmpl<mode>2, *and<mode>3, *and<mode>3_mips16, *ior<mode>3,
>> 	*ior<mode>3_mips16, two unnamed insns after *ior<mode>3_mips16,
>> 	*nor<mode>3, "Combiner patterns to optimize truncate/zero_extend
>> 	combinations", *zero_extend<SHORT:mode><GPR:mode>2,
>> 	*zero_extendqihi2, *extend<SHORT:mode><GPR:mode>2_mips16e,
>> 	*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>, *movdi_64bit,
>> 	*movdi_64bit_mips16, *movsi_internal, *movsi_mips16, movcc,
>> 	*movhi_internal, *movhi_mips16, *movqi_internal, *movqi_mips16,
>> 	*movsf_hardfloat, *movsf_softfloat, *movsf_mips16,
>> 	*movdf_hardfloat_64bit, *movdf_hardfloat_32bit,
>> 	movv2sf_hardfloat_64bit): Use the new types.
>> 	(*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16,
>> 	*movdf_softfloat, *movdf_mips16): Use "multi".
>> 	(extendqihi2): Replace with a define_expand.
>> 	(*extendqihi2_mips16e, *extendqihi2, *extendqihi2_seb): New.
>> 	Based on extend<SHORT:mode><GPR:mode>2 patterns.
>>[...]
>
>   I got one test that failed on the target of mipsisa32r2-elf
> (compiled with -mips32.)  The issue may be from "*extendqihi2"
> where operands[0] is not converted to SImode.
> The test was ok with "gcc version 4.3.0 20070625 (experimental)",
> but not with the current mainline.  Thanks!
>
> Ex:
> # cat bug129.c
> short test(signed char a, signed char b)
> {
>   short c = (short) a;
>   short d = (short) b;
>   short e = c * d;
>   return e;
> }
>
> # mipsisa32r2-elf-gcc -O -mips32 -S bug129.c
> bug129.c: In function â?~testâ?T:
> bug129.c:7: error: unrecognizable insn:
> (insn 28 6 29 2 bug129.c:2 (set (reg:HI 2 $2 [orig:199 b ] [199])
>         (ashift:SI (reg:SI 5 $5 [ b+-7 ])
>             (const_int 24 [0x18]))) -1 (nil))
> bug129.c:7: internal compiler error: in extract_insn, at recog.c:1991
> Please submit a full bug report,
> with preprocessed source if appropriate.
> See <URL:http://gcc.gnu.org/bugs.html> for instructions.

Joseph's away at the moment, so I've installed the fix below after
regression-testing on mipsisa64-elf.

Richard


gcc/
	* config/mips/mips.md (*extendqihi2): Convert the destination
	to SImode.

Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	(revision 176278)
+++ gcc/config/mips/mips.md	(working copy)
@@ -2639,6 +2639,7 @@ (define_insn_and_split "*extendqihi2"
   [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
 {
+  operands[0] = gen_lowpart (SImode, operands[0]);
   operands[1] = gen_lowpart (SImode, operands[1]);
   operands[2] = GEN_INT (GET_MODE_BITSIZE (SImode)
 			 - GET_MODE_BITSIZE (QImode));