[RTL, ColdFire 24/63] Add support for a MODE_INDEX_REG_CLASS macro

[Jeffrey Law]

On Wed, 2007-01-10 at 21:27 +0000, Richard Sandiford wrote:

> Right, that describes the ISA restrictions.  But this patch isn't
> really about the ISA restrictions per se.  The m68k port makes a pragmatic
> decision to forbid indexed addressing modes for _all_ SFmode and DFmode
> MEMs if TARGET_COLDFIRE_FPU, on the basis that the vast majority of
> memory accesses will be in FPU instructions.  We then expose the
> necessary addressing code to the pre-reload optimisers and register
> allocators, rather than leaving reload to find scratch address registers
> from somewhere.  Although I didn't make that decision (it's what current
> mainline does), I can well imagine that it leads to better code.
> 
> In other words, this is entirely an internal gcc thing.  The current
> definition of INDEX_REG_CLASS tricks reload into thinking that indexed
> addressing modes are acceptable SFmode and DFmode memory_operands,
> which they aren't.  It will then use such memories in copy-in and
> copy-out reload instructions.
The fundamental problem is that the m68k port is lying and you're
hacking up reload to deal with the m68k version of the lie.  FWIW,
the PA port lies too, but all the hair of the lie is buried in the
backend.  You might review how the PA handles this situation since
they are quite similar (basically reversed -- the PA has full indexed
addressing modes for loads/stores using FP registers, but not for
integer registers.

Jeff