[PATCH] Fix PR middle-end/28690, indexed load/store performance + reload bug

[Paolo Bonzini]

> Can you explain what the underlying problems with (set X (op Y X)) are?
> Is there one particular idiom (eg, X is a reg and Y is a mem) that is
> important to get the ordering right or do all cases need to be ordered
> right?

Unfortunately, all.

> Also, what does getting the right order do that helps so much?
> Is it that it introduces more optimization opportunities or???

I didn't analyze it much in depth; I just found it when working on 
fwprop.  Looking at the diffs in the RTL, the patched compiler only had 
that difference in the RTL, and the baseline was 10% faster than fwprop. 
  The test case was crafty from SPEC2000 (on i386), file enprise.c.

Paolo