PATCH: fine-tuning for can_store_by_pieces
Nigel Stephens
nigel@mips.com
Tue Aug 21 12:14:00 GMT 2007
Richard Sandiford wrote:
> Nigel Stephens <nigel@mips.com> writes:
>
>> Richard Sandiford wrote:
>>
>>> Sandra Loosemore <sandra@codesourcery.com> writes:
>>>
>>>
>>>> OK, but what I was really asking was, is there a way to *test* for
>>>> situations where we should generate the lui/ori/sw sequences instead
>>>> of the lw/sw? Some combination of TARGET_foo flags and/or the size of
>>>> the string?
>>>>
>>>>
>>> Well, I suppose:
>>>
>>> !optimize_size && !TARGET_MIPS16 && mips_issue_rate () > 1
>>>
>> Many MIPS dual-issue processors are asymettric, and may be able to issue
>> lui, ori and sw down only one pipe or the other -- not both in parallel.
>> So I don't think that testing mips_issue_rate() is sufficient.
>>
>
> True. I suppose I'm biased because all the processors whose schedulers
> I've worked on could issue stores down one pipe and arithmetic
> instructions down the other.
>
>
Your assumption is probably correct, however your schedule for the first
two cycles shows two lui and two ori issuing in parallel, which would
not be possible in such an architecture. For a long enough string though
it could be a win.
> I assume you think we should stick the uncoditional zero here?
>
We could make the STORE_BY_PIECES_P macro dependent on -mtune, and use
the size and alignment to estimate the total cycle count. But zero is
reasonable and we could add a comment suggesting that there's some
opportunity for future tuning on muilti-issue cpus.
Nigel
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