PATCH: Add thumb abssi and neg_abssi patterns

Richard Earnshaw Richard.Earnshaw@buzzard.freeserve.co.uk
Thu Nov 16 09:22:00 GMT 2006


This patch adds abssi2() and neg(abssi2()) patterns for Thumb.  Not much 
else to say except tested on arm-elf cross with no regressions and 
committed to mainline.

2006-11-16  Richard Earnshaw  <rearnsha@arm.com>

	* arm.md (abssi2): Allow Thumb as well.	 Use an SImode scratch for
	Thumb.
	(arm_neg_abssi2): Renamed from neg_abssi2.
	(thumb_abssi2, thumb_neg_abssi2): New patterns with splitters.


-------------- next part --------------
*** config/arm/arm.md	(revision 118920)
--- config/arm/arm.md	(local)
*************** (define_expand "abssi2"
*** 3066,3077 ****
    [(parallel
      [(set (match_operand:SI         0 "s_register_operand" "")
  	  (abs:SI (match_operand:SI 1 "s_register_operand" "")))
!      (clobber (reg:CC CC_REGNUM))])]
!   "TARGET_ARM"
!   "")
  
  (define_insn "*arm_abssi2"
!   [(set (match_operand:SI         0 "s_register_operand" "=r,&r")
  	(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
     (clobber (reg:CC CC_REGNUM))]
    "TARGET_ARM"
--- 3066,3082 ----
    [(parallel
      [(set (match_operand:SI         0 "s_register_operand" "")
  	  (abs:SI (match_operand:SI 1 "s_register_operand" "")))
!      (clobber (match_dup 2))])]
!   "TARGET_EITHER"
!   "
!   if (TARGET_THUMB)
!     operands[2] = gen_rtx_SCRATCH (SImode);
!   else
!     operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
! ")
  
  (define_insn "*arm_abssi2"
!   [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
  	(abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
     (clobber (reg:CC CC_REGNUM))]
    "TARGET_ARM"
*************** (define_insn "*arm_abssi2"
*** 3084,3090 ****
     (set_attr "length" "8")]
  )
  
! (define_insn "*neg_abssi2"
    [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
  	(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
     (clobber (reg:CC CC_REGNUM))]
--- 3089,3109 ----
     (set_attr "length" "8")]
  )
  
! (define_insn_and_split "*thumb_abssi2"
!   [(set (match_operand:SI 0 "s_register_operand" "=l")
! 	(abs:SI (match_operand:SI 1 "s_register_operand" "l")))
!    (clobber (match_scratch:SI 2 "=&l"))]
!   "TARGET_THUMB"
!   "#"
!   "TARGET_THUMB && reload_completed"
!   [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
!    (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
!    (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
!   ""
!   [(set_attr "length" "6")]
! )
! 
! (define_insn "*arm_neg_abssi2"
    [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
  	(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
     (clobber (reg:CC CC_REGNUM))]
*************** (define_insn "*neg_abssi2"
*** 3098,3103 ****
--- 3117,3136 ----
     (set_attr "length" "8")]
  )
  
+ (define_insn_and_split "*thumb_neg_abssi2"
+   [(set (match_operand:SI 0 "s_register_operand" "=l")
+ 	(neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "l"))))
+    (clobber (match_scratch:SI 2 "=&l"))]
+   "TARGET_THUMB"
+   "#"
+   "TARGET_THUMB && reload_completed"
+   [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
+    (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))
+    (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 2)))]
+   ""
+   [(set_attr "length" "6")]
+ )
+ 
  (define_expand "abssf2"
    [(set (match_operand:SF         0 "s_register_operand" "")
  	(abs:SF (match_operand:SF 1 "s_register_operand" "")))]


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