[patch] tuning gcc for Intel Core2

[H. J. Lu]

On Mon, Nov 13, 2006 at 12:01:17PM -0500, Vladimir Makarov wrote:
>  Here is the patch for tuning gcc for Intel Core2 processor.  I did
> about 30 SPEC2000 runs to find good parameters which are practically
> the same what Intel gave and recommended in their optimization guide
> made public a few days ago.
> 
>  The patch increases SPECINT2000 score to 1963 from 1925 (for
> generic) or 1901 (for nocona).  SPECFP2000 sore is the same as for
> generic 1875 (nocona has 1856).  One benchmark (gcc) did particular
> well -- about 20% improvement (1788 for generic tuning vs 2210 for
> core2).  The size of code generated for Core2 is smaller (0.46% for
> SPECInt and 0.54% SPECFp) than one for generic.
> 
>  All measurements were done on 2.66 Ghz Intel Core2 machine.
> 
>  I think DFA for Core2 would increase SPEC scores even more because
> even insn scheduling without the description (using default
> parameters) works well for Core2.  But I have no enough details for
> Core2 to do it.
> 
> Is it ok for the mainline?
> 
> 2006-11-13  Vladimir Makarov  <vmakarov@redhat.com>
> 
> 	* doc/invoke.texi (core2): Add item.
> 
> 	* config/i386/i386.h (TARGET_CORE2, TARGET_CPU_DEFAULT_core2): New
> 	macros.
> 	(TARGET_CPU_CPP_BUILTINS): Add code for core2.
> 	(TARGET_CPU_DEFAULT_generic): Change value.
> 	(TARGET_CPU_DEFAULT_NAMES): Add core2.
> 	(processor_type): Add new constant PROCESSOR_CORE2.
> 
> 	* config/i386/i386.md (cpu): Add core2.
> 
> 	* config/i386/i386.c (core2_cost): New initialized variable.
> 	(m_CORE2): New macro.
> 	(x86_movx, x86_unroll_strlen, x86_cmove, x86_deep_branch,
> 	x86_use_sahf, x86_partial_reg_stall, x86_partial_flag_reg_stall,
> 	x86_use_simode_fiop, x86_single_stringop, x86_himode_math,
> 	x86_promote_hi_regs, x86_sub_esp_4, x86_sub_esp_8, x86_add_esp_4,
> 	x86_add_esp_8, x86_integer_DFmode_moves,
> 	x86_partial_reg_dependency, x86_accumulate_outgoing_args,
> 	x86_prologue_using_move, x86_epilogue_using_move,
> 	x86_arch_always_fancy_math_387, x86_sse_partial_reg_dependency,
> 	x86_sse_load0_by_pxor, x86_rep_movl_optimal,
> 	x86_ext_80387_constants, x86_four_jump_limit, x86_schedule,
> 	x86_pad_returns): Add m_CORE2.
> 	(override_options): Add entries for Core2.
> 	(ix86_issue_rate): Add case for Core2.
> 	
> 

> Index: doc/invoke.texi
> ===================================================================
> --- doc/invoke.texi	(revision 118669)
> +++ doc/invoke.texi	(working copy)
> @@ -9281,6 +9281,9 @@ set support.
>  @item nocona
>  Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
>  SSE2 and SSE3 instruction set support.
> +@item core2
> +Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2 and SSE3
> +instruction set support.

Please add SSSE3.


H.J.