[patch] Make prefetching parameters controlable with --param

H. J. Lu hjl@lucon.org
Mon Nov 13 15:39:00 GMT 2006


On Thu, Nov 09, 2006 at 07:02:41PM -0700, Roger Sayle wrote:
> 
> Hi Zdenek,
> 
> On Thu, 9 Nov 2006, Zdenek Dvorak wrote:
> >
> > 	* params.c (set_param_value): Initialize the "set" field.
> > 	* params.h (struct param_info): Add "set" field.
> > 	(PARAM_SET_P): New macro.
> > 	(PREFETCH_LATENCY, SIMULTANEOUS_PREFETCHES, L1_CACHE_SIZE,
> > 	L1_CACHE_LINE_SIZE): New macros.
> > 	* toplev.c (DEFPARAM): Initialize the "set" field.
> > 	* tree-ssa-loop-prefetch.c (PREFETCH_LATENCY,
> > 	SIMULTANEOUS_PREFETCHES): Removed.
> > 	(PREFETCH_BLOCK): Use L1_CACHE_LINE_SIZE.
> > 	(tree_ssa_prefetch_arrays): Dump the values of the parameters.
> > 	* config/sparc/sparc.c: Include params.h.
> > 	(sparc_override_options): Set SIMULTANEOUS_PREFETCHES and
> > 	L1_CACHE_LINE_SIZE parameters.
> > 	* config/sparc/sparc.h (PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES):
> > 	Removed.
> > 	* config/i386/i386.h (PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES):
> > 	Removed.
> > 	* config/i386/i386.c: Include params.h.
> > 	(k8_cost): Change default value for SIMULTANEOUS_PREFETCHES.
> > 	(override_options): Set SIMULTANEOUS_PREFETCHES and
> > 	L1_CACHE_LINE_SIZE parameters.
> > 	* config/sh/sh.h (SIMULTANEOUS_PREFETCHES): Removed.
> > 	(OPTIMIZATION_OPTIONS): Set SIMULTANEOUS_PREFETCHES and
> > 	L1_CACHE_LINE_SIZE parameters.
> > 	* config/ia64/ia64.c (ia64_optimization_options): Set
> > 	SIMULTANEOUS_PREFETCHES and L1_CACHE_LINE_SIZE parameters.
> > 	* config/ia64/ia64.h (SIMULTANEOUS_PREFETCHES, PREFETCH_BLOCK):
> > 	Removed.
> > 	* params.def (PARAM_PREFETCH_LATENCY, PARAM_SIMULTANEOUS_PREFETCHES,
> > 	PARAM_L1_CACHE_SIZE, PARAM_L1_CACHE_LINE_SIZE): New params.
> 
> 
> This is OK for mainline, but you'll need to update the documentation
> (certainly to describe the new param command line options, but probably
> also to undocument the previous target macros).
> 
> 
> !   /* New AMD processors newer drop prefetches; if they cannot be performed
> s/newer/never/
> 
> !      immediatelly, they are queued.  We set number of simultaneous prefetches
> s/immediatelly/immediately/
> 
> 

I checked in this to fix the typo.


H.J.
---
2006-11-13  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c: Fix a typo in comment.

Index: config/i386/i386.c
===================================================================
--- config/i386/i386.c	(revision 118763)
+++ config/i386/i386.c	(working copy)
@@ -537,7 +537,7 @@
 					   in SImode, DImode and TImode */
   5,					/* MMX or SSE register to integer */
   64,					/* size of prefetch block */
-  /* New AMD processors neer drop prefetches; if they cannot be performed
+  /* New AMD processors never drop prefetches; if they cannot be performed
      immediately, they are queued.  We set number of simultaneous prefetches
      to a large constant to reflect this (it probably is not a good idea not
      to limit number of prefetches at all, as their execution also takes some



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